Sfoglia per Autore  

Opzioni
Mostrati risultati da 41 a 60 di 280
Titolo Data di pubblicazione Autore(i) File
Hot-carrier degradation and oxide charge build-up in self-aligned etched-polysilicon npn bipolar transistors 1-gen-1996 A., Neviani; Pavan, Paolo; A., Chantre; M., Stucchi; T., Tommasin; L., Vendrame; E., Zanoni
SPICE modelling of impact ionisation effects in silicon bipolar transistors 1-gen-1996 Verzellesi, Giovanni; A., Dal Fabbro; Pavan, Paolo; L., Vendrame; E., Zabotto; A., Zanini; A., Chantre; E., Zanoni
Analysis of charge storage in the base of bipolar transistors and its influence on the parasitic resistance adopting an eight terminal Kelvin test structure 1-gen-1996 S., Asti; T., Cavioni; A., Neviani; Pavan, Paolo; M., Stival; L., Vendrame; E., Zanoni
Experimental and Monte Carlo analysis of impact-ionization in AlGaAs/GaAs HBT's 1-gen-1996 Canali, Claudio; Pavan, Paolo; Dicarlo, A; Lugli, P; Malik, R; Manfredi, M; Neviani, A; Vendrame, L; Zanoni, E; Zandler, G.
HBM and CDM ESD stress test results in 0.6 μm CMOS structures 1-gen-1997 G., Meneghesso; N., Grapputo; P., Colombo; M., Brambilla; Pavan, Paolo; E., Zanoni
Effects of ESD protections on latch-up sensitivity of CMOS 4-stripe structures 1-gen-1997 Pavan, Paolo; Pellesi, A; Meneghesso, G; Zanoni, E.
Hot-carrier degradation and oxide charge build-up in self-aligned etched-polysilicon npn bipolar transistors 1-gen-1997 Neviani, A; Pavan, Paolo; Nardi, A; Chantre, A; Vendrame, L; Zanoni, E.
Characterization of CMOS Structures (O.6 urn process) Submitted to HBM and COM ESD Stress Tests 1-gen-1997 Meneghesso, G.; Zanoni, E.; Colombo, P.; Brambilla, M.; Annunziata, R.; Pavan, P.
Flash memory cells - An overview 1-gen-1997 Pavan, Paolo; R., Bez; P., Olivo; E., Zanoni
Characterization of CMOS structures (0.6 um process) submitted to HBM and CDM ESD stress tests 1-gen-1997 G., Meneghesso; Colombo, P.; M., Brambilla; R., Annunziata; Pavan, Paolo; E., Zanoni
Can NROM, a 2 Bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells? 1-gen-1999 Eitan, B.; Pavan, Paolo; Bloom, I.; Aloni, E.; Frommer, A.
Test structures and testing methods for electrostatic discharge: results of PROPHECY project 1-gen-1999 G., Meneghesso; E., Zanoni; A., Gerosa; Pavan, Paolo; W., Stadler; K., Esmark; X., Guggenmos
The Industry Standard Flash Memory Cell 1-gen-1999 Pavan, Paolo; Bez, R.
Endurance optimization in microFlash Memory Device 1-gen-2000 Aloni, E.; Gutman, M.; Roizin, Y.; Finzi, D.; Hyun, C. I.; Bloom, I.; Levy, D.; Lann, A.; Pavan, Paolo
NROM: A novel localized trapping, 2-bit nonvolatile memory cell 1-gen-2000 B., Eitan; Pavan, Paolo; I., Bloom; E., Aloni; A., Frommer; D., Finzi
A new methodology for SEE testing and simulation 1-gen-2000 Pietri, S.; Pavan, Paolo; Iacono, S.; Striccoli, M.
Degradation mechanisms in polysilicon emitter bipolar junction transistors for digital applications 1-gen-2000 L., Vendrame; Pavan, Paolo; G., Corva; A., Nardi; A., Neviani; E., Zanoni
NROM – a new Non Volatile Memory Technology: from Device to Products 1-gen-2001 I., Bloom; Pavan, Paolo; B., Eitan
A New Compact Model of Floating Gate Non-Volatile Memory Cells 1-gen-2001 Larcher, Luca; Pavan, Paolo; F., Gattel; L., Albani; A., Marmiroli
Bias and W/L dependence of capacitive coupling coefficients in floating gate memory cells 1-gen-2001 Larcher, Luca; Pavan, Paolo; L., Albani; T., Ghilardi
Mostrati risultati da 41 a 60 di 280
Legenda icone

  •  file ad accesso aperto
  •  file disponibili sulla rete interna
  •  file disponibili agli utenti autorizzati
  •  file disponibili solo agli amministratori
  •  file sotto embargo
  •  nessun file disponibile