In this paper, we present results on the influence of the turning on of ESD protection devices on the latch-up sensitivity of 0.35 mu m CMOS ICs. Moreover, we will show that layout details and circuit placement do have an influence on latch-up sensitivity, and that the presence of guard-rings greatly improves latch-up hardness.

Effects of ESD protections on latch-up sensitivity of CMOS 4-stripe structures / Pavan, Paolo; Pellesi, A; Meneghesso, G; Zanoni, E.. - In: MICROELECTRONICS RELIABILITY. - ISSN 0026-2714. - STAMPA. - 37:(1997), pp. 1561-1564.

Effects of ESD protections on latch-up sensitivity of CMOS 4-stripe structures

PAVAN, Paolo;
1997

Abstract

In this paper, we present results on the influence of the turning on of ESD protection devices on the latch-up sensitivity of 0.35 mu m CMOS ICs. Moreover, we will show that layout details and circuit placement do have an influence on latch-up sensitivity, and that the presence of guard-rings greatly improves latch-up hardness.
37
1561
1564
Effects of ESD protections on latch-up sensitivity of CMOS 4-stripe structures / Pavan, Paolo; Pellesi, A; Meneghesso, G; Zanoni, E.. - In: MICROELECTRONICS RELIABILITY. - ISSN 0026-2714. - STAMPA. - 37:(1997), pp. 1561-1564.
Pavan, Paolo; Pellesi, A; Meneghesso, G; Zanoni, E.
File in questo prodotto:
Non ci sono file associati a questo prodotto.
Pubblicazioni consigliate

Caricamento pubblicazioni consigliate

Licenza Creative Commons
I metadati presenti in IRIS UNIMORE sono rilasciati con licenza Creative Commons CC0 1.0 Universal, mentre i file delle pubblicazioni sono rilasciati con licenza Attribuzione 4.0 Internazionale (CC BY 4.0), salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11380/8804
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 4
  • ???jsp.display-item.citation.isi??? 3
social impact