Hot-carrier degradation and oxide charge build-up in self-aligned etched-polysilicon npn bipolar transistors

The aim of this paper is to present the results of several accelerated tests performed on self-aligned bipolar transistors with emitter spacers. We show that the problem of lifetime extrapolation is complicated by a strong dependence of degradation kinetics on device layout. We also demonstrate, by means of emission microscopy, that remarkable current crowding effects take place during accelerated testing, especially for tests performed avalanching the base-emitter junction, thus hampering the usual normalization of accelerating factors to device perimeters. A new method for evaluating charge injection in the oxide is described; the method consists in evaluating the decrease in the electric field at the periphery of the device by measuring the temperature dependence of the tunneling reverse base current component.