In this work, we present new results concerning electrostatic discharge (ESD) robustness in 0.6 μm device structure. Devices have been submitted to both HBM and socketed CDM (sCDM) ESD tests. A systematic failure analysis of the stressed structures has been carried out obtaining important information on the dependence of the behaviour of these on layout parameters. Typical LDD MOSFET devices show damages which mainly consist in drain/substrate junction spiking in correspondence of the contacts: breakdown of the less deeper P implant junction (n+-substrate) can be responsible for the observed degradation. Devices having P deeper implant source and drain are more resistant than the previous ones and their failure mechanisms consist in lateral spiking. For some large structures adopting lateral bipolar transistor with or without gate polysilicon over Field oxide technology, SEM analysis and emission microscopy clearly demonstrate that early ESD failures can be attributed to a non uniform current distribution within the structures.

HBM and CDM ESD stress test results in 0.6 μm CMOS structures / G., Meneghesso; N., Grapputo; P., Colombo; M., Brambilla; Pavan, Paolo; E., Zanoni. - STAMPA. - (1997), pp. 704-707. ((Intervento presentato al convegno ESSDERC 97 tenutosi a Stuttgardt, D nel 22-24 sept. 1997.

HBM and CDM ESD stress test results in 0.6 μm CMOS structures

PAVAN, Paolo;
1997-01-01

Abstract

In this work, we present new results concerning electrostatic discharge (ESD) robustness in 0.6 μm device structure. Devices have been submitted to both HBM and socketed CDM (sCDM) ESD tests. A systematic failure analysis of the stressed structures has been carried out obtaining important information on the dependence of the behaviour of these on layout parameters. Typical LDD MOSFET devices show damages which mainly consist in drain/substrate junction spiking in correspondence of the contacts: breakdown of the less deeper P implant junction (n+-substrate) can be responsible for the observed degradation. Devices having P deeper implant source and drain are more resistant than the previous ones and their failure mechanisms consist in lateral spiking. For some large structures adopting lateral bipolar transistor with or without gate polysilicon over Field oxide technology, SEM analysis and emission microscopy clearly demonstrate that early ESD failures can be attributed to a non uniform current distribution within the structures.
ESSDERC 97
Stuttgardt, D
22-24 sept. 1997
704
707
G., Meneghesso; N., Grapputo; P., Colombo; M., Brambilla; Pavan, Paolo; E., Zanoni
HBM and CDM ESD stress test results in 0.6 μm CMOS structures / G., Meneghesso; N., Grapputo; P., Colombo; M., Brambilla; Pavan, Paolo; E., Zanoni. - STAMPA. - (1997), pp. 704-707. ((Intervento presentato al convegno ESSDERC 97 tenutosi a Stuttgardt, D nel 22-24 sept. 1997.
File in questo prodotto:
File Dimensione Formato  
C14.pdf

Accesso riservato

Tipologia: Versione dell'autore revisionata e accettata per la pubblicazione
Dimensione 446.5 kB
Formato Adobe PDF
446.5 kB Adobe PDF   Visualizza/Apri   Richiedi una copia
Pubblicazioni consigliate

Licenza Creative Commons
I metadati presenti in IRIS UNIMORE sono rilasciati con licenza Creative Commons CC0 1.0 Universal, mentre i file delle pubblicazioni sono rilasciati con licenza Attribuzione 4.0 Internazionale (CC BY 4.0), salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/737719
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 0
  • ???jsp.display-item.citation.isi??? ND
social impact