In this work, we present new results concerning electrostatic discharge (ESD) robustness of 0.6 um CMOS structures. Devices have been tested according to both HBM and socketed CDM (sCDM) ESD test procedures. Test structures have been submitted to a complete characterization consisting in: 1) measurement of the tum-on time of the protection structures submitted to pulses with very fast rise times; 2) ESD stress test with the HBM and sCDM models; 3) failure analysis based on emission microscopy (EMMI) and Scanning Electron Microscopy (SEM).
Characterization of CMOS Structures (O.6 urn process) Submitted to HBM and COM ESD Stress Tests / Meneghesso, G.; Zanoni, E.; Colombo, P.; Brambilla, M.; Annunziata, R.; Pavan, P.. - 1997-:(1997), pp. 315-320. (Intervento presentato al convegno 23rd International Symposium for Testing and Failure Analysis, ISTFA 1997 tenutosi a usa nel 0199) [10.31399/asm.cp.istfa1997p0315].
Characterization of CMOS Structures (O.6 urn process) Submitted to HBM and COM ESD Stress Tests
Zanoni E.;Pavan P.
1997
Abstract
In this work, we present new results concerning electrostatic discharge (ESD) robustness of 0.6 um CMOS structures. Devices have been tested according to both HBM and socketed CDM (sCDM) ESD test procedures. Test structures have been submitted to a complete characterization consisting in: 1) measurement of the tum-on time of the protection structures submitted to pulses with very fast rise times; 2) ESD stress test with the HBM and sCDM models; 3) failure analysis based on emission microscopy (EMMI) and Scanning Electron Microscopy (SEM).
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