A comparison between two recently proposed DC methods for the extraction of base parasitic resistance in double-base Kelvin-tapped Bipolar Junction Transistors has been performed, based on both measurement and numerical device simulation. Discrepancies in the results given by the two methods in medium and high injection regimes are shown, and the need to take into account majority carrier density modulation in the quasi-neutral base region is demonstrated. A new method for the extraction of the extrinsic component of the base resistance is proposed, based on a simple biasing scheme of the eight-terminal device.

Analysis of charge storage in the base of bipolar transistors and its influence on the parasitic resistance adopting an eight terminal Kelvin test structure / S., Asti; T., Cavioni; A., Neviani; Pavan, Paolo; M., Stival; L., Vendrame; E., Zanoni. - STAMPA. - (1996), pp. 91-96. ((Intervento presentato al convegno IEEE International Conference on Microelectronic Test Structures tenutosi a Trento, I nel March 25-28, 1996.

Analysis of charge storage in the base of bipolar transistors and its influence on the parasitic resistance adopting an eight terminal Kelvin test structure

PAVAN, Paolo;
1996-01-01

Abstract

A comparison between two recently proposed DC methods for the extraction of base parasitic resistance in double-base Kelvin-tapped Bipolar Junction Transistors has been performed, based on both measurement and numerical device simulation. Discrepancies in the results given by the two methods in medium and high injection regimes are shown, and the need to take into account majority carrier density modulation in the quasi-neutral base region is demonstrated. A new method for the extraction of the extrinsic component of the base resistance is proposed, based on a simple biasing scheme of the eight-terminal device.
IEEE International Conference on Microelectronic Test Structures
Trento, I
March 25-28, 1996
91
96
S., Asti; T., Cavioni; A., Neviani; Pavan, Paolo; M., Stival; L., Vendrame; E., Zanoni
Analysis of charge storage in the base of bipolar transistors and its influence on the parasitic resistance adopting an eight terminal Kelvin test structure / S., Asti; T., Cavioni; A., Neviani; Pavan, Paolo; M., Stival; L., Vendrame; E., Zanoni. - STAMPA. - (1996), pp. 91-96. ((Intervento presentato al convegno IEEE International Conference on Microelectronic Test Structures tenutosi a Trento, I nel March 25-28, 1996.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/737726
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