Sfoglia per Autore PADOVANI, ANDREA
Temperature Monitor: a New Tool to Profile Charge Distribution in NROMTM Memory Devices
2006 L., Avital; Padovani, Andrea; Larcher, Luca; I., Bloom; R., Arie; Pavan, Paolo; B., Eitan
Profiling charge distribution in NROM devices
2006 Padovani, Andrea; Larcher, Luca; Pavan, Paolo
Monte-Carlo Simulations of Flash Memory Array Retention
2007 Padovani, Andrea; Larcher, Luca; A., Chimenton; Pavan, Paolo
Statistical Methodologies for Integrated Circuits Design
2007 Padovani, Andrea; A., Chimenton; P., Olivo; P., Fantini; L., Vendrame; S., Mennillo
Hole Distributions in NROM Devices: Profiling Technique and Correlation to Memory Retention
2007 Padovani, Andrea; Larcher, Luca; Pavan, Paolo
Modeling NAND Flash memories for circuit simulations
2007 Larcher, Luca; Padovani, Andrea; I., Rimmaudo; Pavan, Paolo; A., Calderoni; G., Molteni; F., Gattel; P., Fantini
ID-VGS Based Tools to Profile Charge Distributions on NROMTM Memory Devices
2007 Padovani, Andrea; Larcher, Luca; Pavan, Paolo; L., Avital; I., Bloom; B., Eitan
Dielectric Reliability for Future Logic and Non-Volatile Memory Applications: a Statistical Simulation Analysis Approach
2007 Padovani, Andrea; Larcher, Luca; A., Chimenton; Pavan, Paolo; P., Olivo
Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric
2008 G., Bersuker; D., Heh; C., Young; H., Park; P., Khanal; Larcher, Luca; Padovani, Andrea; P., Lenahan; J., Ryan; B. H., Lee; H., Tseng; R., Jammy
Statistical modeling of leakage currents through SiO2/high- κ dielectrics stacks for non-volatile memory applications
2008 Padovani, A.; Larcher, L.; Verma, S.; Pavan, P.; Majhi, P.; Kapur, P.; Parat, K.; Bersuker, G.; Saraswat, K.
Hole Distributions in Erased NROM Devices: profiling method and effects on reliability
2008 Padovani, Andrea; Larcher, Luca; Pavan, Paolo
On the RESET-SET transition in Phase Change Memories
2008 G., Puzzilli; F., Irrera; Padovani, Andrea; Pavan, Paolo; Larcher, Luca; A., Arya; DELLA MARCA, Vincenzo; A., Pirovano
Feasibility of SIO2/Al2O3 tunnel dielectric for future Flash memories generations
2008 Padovani, Andrea; Larcher, Luca; S., Verma; Pavan, Paolo; P., Majhi; P., Kapur; K., Parat; G., Bersuker; K., Saraswat
Modeling NAND Flash Memories for IC Design
2008 Larcher, Luca; Padovani, Andrea; Pavan, Paolo; P., Fantini; A., Calderoni; A., Mauri; A., Benvenuti
Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing
2009 Morassi, Luca; Larcher, Luca; L., Pantisano; Padovani, Andrea; R., Degreave; M. B., Zahid; B. J., O'Sullivan
Understanding endurance degradation in Flash memory through transconductance measurement
2009 S., Verma; G., Bersuker; D. C., Gilmer; Padovani, Andrea; H., Park; A., Nainani; J., Huang; K., Parat; P. D., Kirsch; Larcher, Luca; H. H., Tseng; K. C. Saraswat R., Jammy
Connecting electrical and structural dielectric characteristics
2009 G., Bersuker; D., Veksler; C. D., Young; H., Park; Morassi, Luca; Padovani, Andrea; Larcher, Luca; W., Taylor; P. D., Kirsch; R., Jammy
Modeling TANOS Memory Program Transients to Investigate Charge Trapping Dynamics
2009 Padovani, Andrea; Larcher, Luca; D., Heh; G., Bersuker
A technique to extract high-k IPD stack layer thicknesses from C-V measurements
2009 Larcher, Luca; Pavan, Paolo; Padovani, Andrea; G., Ghidini
A Novel Fluorine Incorporated Band Engineered (BE) Tunnel (SiO2/ HfSiO/ SiO2) TANOS with Excellent Program/Erase & Endurance to 10^5 Cycles
2009 S., Verma; G., Bersuker; D. C., Gilmer; Padovani, Andrea; P., Hokyung; A., Nainani; D., Heh; J., Huang; J., Jiang; K., Parat; P. D., Kirsch; Larcher, Luca; Hsing Huang, Tseng; K. C., Saraswat; R., Jammy
Titolo | Data di pubblicazione | Autore(i) | File |
---|---|---|---|
Temperature Monitor: a New Tool to Profile Charge Distribution in NROMTM Memory Devices | 1-gen-2006 | L., Avital; Padovani, Andrea; Larcher, Luca; I., Bloom; R., Arie; Pavan, Paolo; B., Eitan | |
Profiling charge distribution in NROM devices | 1-gen-2006 | Padovani, Andrea; Larcher, Luca; Pavan, Paolo | |
Monte-Carlo Simulations of Flash Memory Array Retention | 1-gen-2007 | Padovani, Andrea; Larcher, Luca; A., Chimenton; Pavan, Paolo | |
Statistical Methodologies for Integrated Circuits Design | 1-gen-2007 | Padovani, Andrea; A., Chimenton; P., Olivo; P., Fantini; L., Vendrame; S., Mennillo | |
Hole Distributions in NROM Devices: Profiling Technique and Correlation to Memory Retention | 1-gen-2007 | Padovani, Andrea; Larcher, Luca; Pavan, Paolo | |
Modeling NAND Flash memories for circuit simulations | 1-gen-2007 | Larcher, Luca; Padovani, Andrea; I., Rimmaudo; Pavan, Paolo; A., Calderoni; G., Molteni; F., Gattel; P., Fantini | |
ID-VGS Based Tools to Profile Charge Distributions on NROMTM Memory Devices | 1-gen-2007 | Padovani, Andrea; Larcher, Luca; Pavan, Paolo; L., Avital; I., Bloom; B., Eitan | |
Dielectric Reliability for Future Logic and Non-Volatile Memory Applications: a Statistical Simulation Analysis Approach | 1-gen-2007 | Padovani, Andrea; Larcher, Luca; A., Chimenton; Pavan, Paolo; P., Olivo | |
Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric | 1-gen-2008 | G., Bersuker; D., Heh; C., Young; H., Park; P., Khanal; Larcher, Luca; Padovani, Andrea; P., Lenahan; J., Ryan; B. H., Lee; H., Tseng; R., Jammy | |
Statistical modeling of leakage currents through SiO2/high- κ dielectrics stacks for non-volatile memory applications | 1-gen-2008 | Padovani, A.; Larcher, L.; Verma, S.; Pavan, P.; Majhi, P.; Kapur, P.; Parat, K.; Bersuker, G.; Saraswat, K. | |
Hole Distributions in Erased NROM Devices: profiling method and effects on reliability | 1-gen-2008 | Padovani, Andrea; Larcher, Luca; Pavan, Paolo | |
On the RESET-SET transition in Phase Change Memories | 1-gen-2008 | G., Puzzilli; F., Irrera; Padovani, Andrea; Pavan, Paolo; Larcher, Luca; A., Arya; DELLA MARCA, Vincenzo; A., Pirovano | |
Feasibility of SIO2/Al2O3 tunnel dielectric for future Flash memories generations | 1-gen-2008 | Padovani, Andrea; Larcher, Luca; S., Verma; Pavan, Paolo; P., Majhi; P., Kapur; K., Parat; G., Bersuker; K., Saraswat | |
Modeling NAND Flash Memories for IC Design | 1-gen-2008 | Larcher, Luca; Padovani, Andrea; Pavan, Paolo; P., Fantini; A., Calderoni; A., Mauri; A., Benvenuti | |
Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing | 1-gen-2009 | Morassi, Luca; Larcher, Luca; L., Pantisano; Padovani, Andrea; R., Degreave; M. B., Zahid; B. J., O'Sullivan | |
Understanding endurance degradation in Flash memory through transconductance measurement | 1-gen-2009 | S., Verma; G., Bersuker; D. C., Gilmer; Padovani, Andrea; H., Park; A., Nainani; J., Huang; K., Parat; P. D., Kirsch; Larcher, Luca; H. H., Tseng; K. C. Saraswat R., Jammy | |
Connecting electrical and structural dielectric characteristics | 1-gen-2009 | G., Bersuker; D., Veksler; C. D., Young; H., Park; Morassi, Luca; Padovani, Andrea; Larcher, Luca; W., Taylor; P. D., Kirsch; R., Jammy | |
Modeling TANOS Memory Program Transients to Investigate Charge Trapping Dynamics | 1-gen-2009 | Padovani, Andrea; Larcher, Luca; D., Heh; G., Bersuker | |
A technique to extract high-k IPD stack layer thicknesses from C-V measurements | 1-gen-2009 | Larcher, Luca; Pavan, Paolo; Padovani, Andrea; G., Ghidini | |
A Novel Fluorine Incorporated Band Engineered (BE) Tunnel (SiO2/ HfSiO/ SiO2) TANOS with Excellent Program/Erase & Endurance to 10^5 Cycles | 1-gen-2009 | S., Verma; G., Bersuker; D. C., Gilmer; Padovani, Andrea; P., Hokyung; A., Nainani; D., Heh; J., Huang; J., Jiang; K., Parat; P. D., Kirsch; Larcher, Luca; Hsing Huang, Tseng; K. C., Saraswat; R., Jammy |
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