In this paper, we investigate the feasibility of SiO2/Al2O3 stack tunnel dielectric for future Flash memory generations using statistical leakage current simulations. We show that the statistical Monte Carlo (MC) simulator we employed reproduces accurately leakage currents measured on SiO2/Al2O3 dielectric capacitors. Exploiting its statistical capabilities, we calculate leakage current distributions in Flash memory retention conditions. We show that the high defectiveness of AI2O3 stacks strongly reduces the potential improvement of Flash retention due to the introduction of AI2O3 tunnel dielectric.

Feasibility of SIO2/Al2O3 tunnel dielectric for future Flash memories generations / Padovani, Andrea; Larcher, Luca; S., Verma; Pavan, Paolo; P., Majhi; P., Kapur; K., Parat; G., Bersuker; K., Saraswat. - STAMPA. - (2008), pp. 111-114. ((Intervento presentato al convegno 9th Ultimate Integration on Silicon Conference (IEEE ULIS) tenutosi a Udine, Italy nel 12-14 March 2008.

Feasibility of SIO2/Al2O3 tunnel dielectric for future Flash memories generations

PADOVANI, ANDREA;LARCHER, Luca;PAVAN, Paolo;
2008-01-01

Abstract

In this paper, we investigate the feasibility of SiO2/Al2O3 stack tunnel dielectric for future Flash memory generations using statistical leakage current simulations. We show that the statistical Monte Carlo (MC) simulator we employed reproduces accurately leakage currents measured on SiO2/Al2O3 dielectric capacitors. Exploiting its statistical capabilities, we calculate leakage current distributions in Flash memory retention conditions. We show that the high defectiveness of AI2O3 stacks strongly reduces the potential improvement of Flash retention due to the introduction of AI2O3 tunnel dielectric.
9th Ultimate Integration on Silicon Conference (IEEE ULIS)
Udine, Italy
12-14 March 2008
111
114
Padovani, Andrea; Larcher, Luca; S., Verma; Pavan, Paolo; P., Majhi; P., Kapur; K., Parat; G., Bersuker; K., Saraswat
Feasibility of SIO2/Al2O3 tunnel dielectric for future Flash memories generations / Padovani, Andrea; Larcher, Luca; S., Verma; Pavan, Paolo; P., Majhi; P., Kapur; K., Parat; G., Bersuker; K., Saraswat. - STAMPA. - (2008), pp. 111-114. ((Intervento presentato al convegno 9th Ultimate Integration on Silicon Conference (IEEE ULIS) tenutosi a Udine, Italy nel 12-14 March 2008.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/590235
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