In this paper, we present a physically-based Monte-Carlo (MC) model reproducing the leakage current flowing across typical dielectric layers (SiO2, high-k) used in ULSI technologies. Simulations will be shown to predict accurately currents measured on MOSFETs, large area MOS capacitor, and tunnel oxides of Flash memories after electrical and radiation stresses. Statistical aspects related to leakage current and threshold voltage are reproduced correctly, allowing worst case corner prediction, necessary to assess dielectric damaging effects on logic circuits and non-volatile memory operation.
Dielectric Reliability for Future Logic and Non-Volatile Memory Applications: a Statistical Simulation Analysis Approach / Padovani, Andrea; Larcher, Luca; A., Chimenton; Pavan, Paolo; P., Olivo. - In: JOURNAL OF THE ELECTROCHEMICAL SOCIETY. - ISSN 0013-4651. - STAMPA. - 8:1(2007), pp. 237-242. (Intervento presentato al convegno 2007 International Conference on SemiconductorTechnology for Ultra Large Scale Integrated Circuits and Thin Film Transistors, ULSIC vs. TFT tenutosi a Barga, ita nel 2007) [10.1149/1.2767314].