Endurance degradation is a limitation for implementing futurescaled flash memory devices. This degradation is mainly attributableto Si/SiO2 interface traps generated during program/erase (P/E) stress rather than fixed charges in the bulk oxide. In this work, we use Gm (transconductance) to monitor the interface degradation. Wereport that interface defect generation is highest during erase operation. In addition to the interface, hole & electron tunnelingprobability seem crucial to degradation during erase. Fluorine incorporation in tunnel stack is found to reduce Gm degradationsuggesting improved interface.
Understanding endurance degradation in Flash memory through transconductance measurement / S., Verma; G., Bersuker; D. C., Gilmer; Padovani, Andrea; H., Park; A., Nainani; J., Huang; K., Parat; P. D., Kirsch; Larcher, Luca; H. H., Tseng; K. C. Saraswat R., Jammy. - STAMPA. - (2009), pp. 1-2. (Intervento presentato al convegno 6th International Symposium on Advanced Gate Stack Technology tenutosi a San Francisco, California, USA nel August 23-26, 2009).
Understanding endurance degradation in Flash memory through transconductance measurement
PADOVANI, ANDREA;LARCHER, Luca;
2009
Abstract
Endurance degradation is a limitation for implementing futurescaled flash memory devices. This degradation is mainly attributableto Si/SiO2 interface traps generated during program/erase (P/E) stress rather than fixed charges in the bulk oxide. In this work, we use Gm (transconductance) to monitor the interface degradation. Wereport that interface defect generation is highest during erase operation. In addition to the interface, hole & electron tunnelingprobability seem crucial to degradation during erase. Fluorine incorporation in tunnel stack is found to reduce Gm degradationsuggesting improved interface.
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