We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-κ dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-κ's traps on leakage current distribution for Flash memory applications. We demonstrate that the high defectiveness typical of high-k materials strongly reduces the potential improvement due to the introduction of band-gap engineered high-κ tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-κ tunnel stacks and to improve technology- reliability issues related to Flash memory applications. © 2008 IEEE.

Statistical modeling of leakage currents through SiO2/high- κ dielectrics stacks for non-volatile memory applications / Padovani, A.; Larcher, L.; Verma, S.; Pavan, P.; Majhi, P.; Kapur, P.; Parat, K.; Bersuker, G.; Saraswat, K.. - (2008), pp. 616-620. ((Intervento presentato al convegno 46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS tenutosi a Phoenix, AZ, usa nel 2008 [10.1109/RELPHY.2008.4558955].

Statistical modeling of leakage currents through SiO2/high- κ dielectrics stacks for non-volatile memory applications

Padovani A.;Larcher L.;Pavan P.;
2008-01-01

Abstract

We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-κ dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-κ's traps on leakage current distribution for Flash memory applications. We demonstrate that the high defectiveness typical of high-k materials strongly reduces the potential improvement due to the introduction of band-gap engineered high-κ tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-κ tunnel stacks and to improve technology- reliability issues related to Flash memory applications. © 2008 IEEE.
46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS
Phoenix, AZ, usa
2008
616
620
Padovani, A.; Larcher, L.; Verma, S.; Pavan, P.; Majhi, P.; Kapur, P.; Parat, K.; Bersuker, G.; Saraswat, K.
Statistical modeling of leakage currents through SiO2/high- κ dielectrics stacks for non-volatile memory applications / Padovani, A.; Larcher, L.; Verma, S.; Pavan, P.; Majhi, P.; Kapur, P.; Parat, K.; Bersuker, G.; Saraswat, K.. - (2008), pp. 616-620. ((Intervento presentato al convegno 46th Annual 2008 IEEE International Reliability Physics Symposium, IRPS tenutosi a Phoenix, AZ, usa nel 2008 [10.1109/RELPHY.2008.4558955].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1248187
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