ESSENI, DAVID

ESSENI, DAVID  

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Risultati 1 - 20 di 32 (tempo di esecuzione: 0.036 secondi).
Titolo Data di pubblicazione Autore(i) File
A New Model for the Backscatter Coefficient in Nanoscale MOSFETs 1-gen-2010 J. L. P. J., van der Steen; Palestri, Pierpaolo; Esseni, David; R. J. E., Hueting
A review of selected topics in physics based modeling for tunnel field-effect transistors 1-gen-2017 Esseni, David; Pala, Marco; Palestri, Pierpaolo; Alper, Cem; Rollo, Tommaso
A virtual III-V Tunnel FET technology platform for ultra-low voltage comparators and level shifters 1-gen-2017 Settino, F.; Lanuzza, M.; Strangio, S.; Crupi, F.; Palestri, Pierpaolo; Esseni, David
Applicability of Macroscopic Transport Models to Decananometer MOSFETs 1-gen-2012 Vasicek, M; Cervenka, J; Esseni, David; Palestri, Pierpaolo; Grasser, P.
Benchmarking of 3-D MOSFET Architectures: Focus on the Impact of Surface Roughness and Self-Heating 1-gen-2018 Badami, O.; Lizzit, D.; Driussi, F.; Palestri, P.; Esseni, D.
Comparison of BULK and Ultra-Thin Double Gate SOI MOSFETs for the 65 nm Technology Node: A Monte Carlo Study 1-gen-2005 M., Braccioli; S., Eminente; Palestri, Pierpaolo; Esseni, David; C., Fiegna
Device Modeling 1-gen-2007 Esseni, David; Palestri, Pierpaolo; Sangiorgi, E.
Drain Current Improvements in Uniaxially Strained p-MOSFETs: a Multi-Subband Monte Carlo Study 1-gen-2008 Conzatti, Francesco; DE MICHIELIS, Marco; Esseni, David; Palestri, Pierpaolo
Drain current improvements in uniaxially strained p-MOSFETs: A Multi-Subband Monte Carlo study 1-gen-2009 Conzatti, Francesco; DE MICHIELIS, Marco; Esseni, David; Palestri, Pierpaolo
Early assessment of tunnel-FET for energy-efficient logic circuits 1-gen-2016 Crupi, Felice; Strangio, Sebastiano; Palestri, Pierpaolo; Lanuzza, Marco; Esseni, David
Editorial: Letters from the 8th Joint International EUROSOI workshop and International Conference on Ultimate Integration on Silicon 1-gen-2022 Driussi, F.; Esseni, D.; Lizzit, D.; Palestri, P.
Editorial: Selected papers from the 8th Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2022) 1-gen-2023 Driussi, F.; Esseni, D.; Lizzit, D.; Palestri, P.
Effect of the Grid Size on the Stability of Self-Consistent Monte-Carlo Simulations 1-gen-2005 N., Barin; Palestri, Pierpaolo; Esseni, David; C., Fiegna
Electromechanical Piezoresistive Sensing in Suspended Graphene Membranes 1-gen-2013 Smith, A. D.; Niklaus, F; Paussa, Alan; Vaziri, S; Fischer, A. C.; Sterner, M; Forsberg, M; Delin, A; Esseni, David; Palestri, Pierpaolo; Ostling, M; Lemme, M. C.
Failure of the Scalar Dielectric Function Approach for the Screening Modeling in Double-Gate SOI MOSFETs and in FinFETs 1-gen-2010 Toniutti, Paolo; Esseni, David; Palestri, Pierpaolo
Full Band and Approximated Solutions of the Schr\"odinger Equation in Silicon Inversion Layers 1-gen-2004 Esseni, David; Palestri, Pierpaolo
Full-Band Quantization Analysis Reveals a Third Valley in Silicon Inversion Layers 1-gen-2005 Esseni, David; Palestri, Pierpaolo
Improved understanding of metal–graphene contacts 1-gen-2019 Driussi, F.; Venica, S.; Gahoi, A.; Gambi, A.; Giannozzi, P.; Kataria, S.; Lemme, M. C.; Palestri, P.; Esseni, D.
Linear combination of bulk bands method for investigating the low-dimensional electron gas in nanostructured devices 1-gen-2005 Esseni, David; Palestri, Pierpaolo
Mixed Tunnel-FET/MOSFET Level Shifters: A New Proposal to Extend the Tunnel-FET Application Domain 1-gen-2015 Lanuzza, Marco; Strangio, Sebastiano; Crupi, Felice; Palestri, Pierpaolo; Esseni, David