Experimental and Numerical Analysis of OFFState Bias Induced Instabilities in Vertical GaNon-Si Trench MOSFETs

We analyzed the threshold-voltage dynamic instabilities induced by OFF-state stress in pseudo-vertical GaN-on-Si Trench MOSFETs (TMOS). Extensive measurements revealed that OFF-state stress experiments induce a progressive increase of threshold voltage (VT), that is fully recoverable only after high-temperature cycles, so that it can appear as permanent degradation at room temperature. VT increase is found to be strongly affected by drain bias and negligibly influenced by gate bias (below threshold). Activation energy (EA) extracted from high- temperature VT recovery experiments was determined to be ≈1 eV. We further characterized pseudo-vertical p-n junction diodes fabricated onto the same wafer as the TMOS’s by means of capacitance iso-thermal spectroscopy (C-ITS). This experiment revealed depletion capacitance (CDEP) instabilities with the same EA as that characterizing the VT instability, leading to the conclusion that trap states present in the epitaxy are the cause of both observations. Numerical device simulations guided the physical interpretation of the observed phenomena, i.e., that donor traps at 1 eV from the conduction band and localized in the p-layer can lead to both VT and CDEP instabilities in the TMOS and in the p-n diode, respectively, by dynamically modulating the effective p-type doping density in the former and the effective depletion layer width in the latter.