We explore, by full 3D numerical simulations, the impact of a few device design solutions on the performance of LDMOS finFETs fabricated in advanced technology nodes (<16 nm). We focus on the impact of the additional (dummy) gates required by lithography loading constraints along the drift region. A few metrics relevant for performance and reliability assessments (specific-on resistance, transition frequency, carrier generation rate and impact ionization current) are examined for different gates’ biasing schemes. The results suggest that a carefully chosen fixed biasing could provide improvements in reliability and in static metrics with low reduction of the dynamic performance.

On the design of LDMOS finFETs in advanced technology nodes / Ruggieri, Alessandro; Tondelli, Lisa; Asanovski, Ruben; Selmi, Luca. - (2024). (Intervento presentato al convegno SIE 2024 tenutosi a Genova nel 26/06/2024-28/06/2024).

On the design of LDMOS finFETs in advanced technology nodes

Alessandro Ruggieri
;
Lisa Tondelli;Ruben Asanovski;Luca Selmi
2024

Abstract

We explore, by full 3D numerical simulations, the impact of a few device design solutions on the performance of LDMOS finFETs fabricated in advanced technology nodes (<16 nm). We focus on the impact of the additional (dummy) gates required by lithography loading constraints along the drift region. A few metrics relevant for performance and reliability assessments (specific-on resistance, transition frequency, carrier generation rate and impact ionization current) are examined for different gates’ biasing schemes. The results suggest that a carefully chosen fixed biasing could provide improvements in reliability and in static metrics with low reduction of the dynamic performance.
2024
SIE 2024
Genova
26/06/2024-28/06/2024
Ruggieri, Alessandro; Tondelli, Lisa; Asanovski, Ruben; Selmi, Luca
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1360066
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