In this paper we present TCAD simulation and experimental results on the influence of interface and border traps on the electrical characteristics of InGaAs quantum-well MOSFETs. These results show that border traps limit the maximum ION, induce a hysteresis in the quasi-static transfer characteristics, and markedly affect CV measurements, inducing a large increase in the accumulation capacitance even at high frequencies where trap effects are commonly assumed to be negligible. The latter effect is particularly insidious from the technologist's perspective, since it can partially compensate quantum capacitance reduction effects, leading to CV data misinterpretation. Interface traps affect mainly the subthreshold slope of IV characteristics and cause frequency dispersion under depletion conditions. Finally, we show that channel mobility extracted by means of the split-CV method is affected by spurious contributions to the gate charge related to both interface and border traps, resulting in channel mobility underestimation.
Effects of Border Traps on Transfer Curve Hysteresis and Split-CV Mobility Measurement in InGaAs Quantum-Well MOSFETs / Pavan, Paolo; Zagni, Nicolo'; Puglisi, Francesco Maria; Alian, Alireza; Thean, Aaron Voon Yew; Collaert, Nadine; Verzellesi, Giovanni. - (2016). (Intervento presentato al convegno 2016 Compound Semiconductor Week, CSW 2016 tenutosi a Toyama (Japan) nel 26-30 June 2016) [10.1109/ICIPRM.2016.7528574].