We report on a methodology to assist fabrication process development using a case study of high thermal budget (HTB) and low thermal budget (LTB) fabrication flows for high- k/metal gate stacks in n-MOSFETs. This methodology is supported by simulations that self-consistently extract defect characteristics by simultaneously considering a set of electrical measurement data, specifically stress-induced leakage current (SILC), threshold voltage shift (PBTI), and multi-frequency charge-pumping (MFCP). The contributions of pre-existing and stress-induced defects in SiO2/HfO2 gate stacks on device performance are examined. Information on defect distributions, extracted in the as-fabricated and post-stress HTB and LTB devices, allow understanding their dependence on the fabrication process, which can provide guidelines for the process optimization.
Defect density evaluation in a high-k MOSFET gate stack combining experimental and modeling methods / Puglisi, Francesco Maria; Veksler, D.; Matthews, K.; Bersuker, G.; Larcher, Luca; Padovani, Andrea; Vandelli, Luca; Pavan, Paolo. - ELETTRONICO. - (2014), pp. GD.4.1-GD.4.4. (Intervento presentato al convegno International Reliability Physics Symposium tenutosi a Waikoloa (HI), USA nel June 1-5, 2014) [10.1109/IRPS.2014.6861147].