In this paper, we use 2D numerical device simulations [Sentaurus Device, Synopsys Inc.] to investigate the impact of interface traps on the electrical characteristics of MOSFETs and MOSHEMTs with InGaAs channel and high-k gate dielectrics. More specifically, the following two technologies are taken into consideration: A) self-aligned inversion-type InGaAs/ZrO2 MOSFETs; B) implant-free InGaAs/Al2O3 MOSHEMTs.
Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics / Morassi, Luca; Padovani, Andrea; Verzellesi, Giovanni; D., Veksler; I., Ok; G., Bersuker. - STAMPA. - (2010), pp. 1-2. (Intervento presentato al convegno 19th European Workshop on Heterostructure Technology (HETECH) tenutosi a Fodele, Crete, Grecia nel 18-20 October 2010).
Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics
MORASSI, LUCA;PADOVANI, ANDREA;VERZELLESI, Giovanni;
2010
Abstract
In this paper, we use 2D numerical device simulations [Sentaurus Device, Synopsys Inc.] to investigate the impact of interface traps on the electrical characteristics of MOSFETs and MOSHEMTs with InGaAs channel and high-k gate dielectrics. More specifically, the following two technologies are taken into consideration: A) self-aligned inversion-type InGaAs/ZrO2 MOSFETs; B) implant-free InGaAs/Al2O3 MOSHEMTs.
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