Charge trapping (CT) memories could be a promising technology option for further NAND Flash scaling. The assessment of the scalability limits and ultimate performances of this technology demands for the comprehensive understanding of the physical mechanisms governing device operation and reliability, which requires accurate physics-based models reproducing the electrical device characteristics. The basic features of the models presented in the literature for CT memory devices are reviewed, underlining theirsimilarities and differences, and highlighting their importance in order to achieve a comprehensive understanding of the physical mechanisms responsible for CT device operation and reliability. A physical model describing the charge transport in nitride and high-j stacks is also presented, which allows gaining further insights into reliability issues related to charge localization and high-j tunnel and blocking dielectrics, like the effects of the blocking alumina layer and the band-gap engineered tunnel dielectrics on the TANOS device retention.

Charge transport in high-k stacks for charge-trapping memory applications: A modeling perspective (invited) / Larcher, Luca; Padovani, Andrea; Vandelli, Luca; Pavan, Paolo. - In: MICROELECTRONIC ENGINEERING. - ISSN 0167-9317. - STAMPA. - 88:7(2011), pp. 1168-1173. [10.1016/j.mee.2011.03.038]

Charge transport in high-k stacks for charge-trapping memory applications: A modeling perspective (invited)

LARCHER, Luca;PADOVANI, ANDREA;VANDELLI, LUCA;PAVAN, Paolo
2011

Abstract

Charge trapping (CT) memories could be a promising technology option for further NAND Flash scaling. The assessment of the scalability limits and ultimate performances of this technology demands for the comprehensive understanding of the physical mechanisms governing device operation and reliability, which requires accurate physics-based models reproducing the electrical device characteristics. The basic features of the models presented in the literature for CT memory devices are reviewed, underlining theirsimilarities and differences, and highlighting their importance in order to achieve a comprehensive understanding of the physical mechanisms responsible for CT device operation and reliability. A physical model describing the charge transport in nitride and high-j stacks is also presented, which allows gaining further insights into reliability issues related to charge localization and high-j tunnel and blocking dielectrics, like the effects of the blocking alumina layer and the band-gap engineered tunnel dielectrics on the TANOS device retention.
2011
88
7
1168
1173
Charge transport in high-k stacks for charge-trapping memory applications: A modeling perspective (invited) / Larcher, Luca; Padovani, Andrea; Vandelli, Luca; Pavan, Paolo. - In: MICROELECTRONIC ENGINEERING. - ISSN 0167-9317. - STAMPA. - 88:7(2011), pp. 1168-1173. [10.1016/j.mee.2011.03.038]
Larcher, Luca; Padovani, Andrea; Vandelli, Luca; Pavan, Paolo
File in questo prodotto:
Non ci sono file associati a questo prodotto.
Pubblicazioni consigliate

Licenza Creative Commons
I metadati presenti in IRIS UNIMORE sono rilasciati con licenza Creative Commons CC0 1.0 Universal, mentre i file delle pubblicazioni sono rilasciati con licenza Attribuzione 4.0 Internazionale (CC BY 4.0), salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/655641
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 7
  • ???jsp.display-item.citation.isi??? 6
social impact