High-electric-field degradation phenomena are investigated in GaN-capped AlGaN-GaN HEMTs by comparing experimental data with numerical device simulations. 150-hour DC stresses were carried out under power-state and off-state conditions. Degradations effects characterizing both stress experiments were: a drop in the DC drain current, the amplification of gate-lag effects, and a decrease in the reverse gate leakage current. Numerical simulations indicate that the simultaneous generation of surface (and/or barrier) traps and of buffer traps can account for all of the above degradation modes. Experiments showed also that the power-state stress induced a drop in the transconductance at high gate-source voltages only, whereas the off-state stress led to a uniform transconductance drop over the entire gate-source-voltage range. This behavior can be reproduced by simulations provided that, under power-state stress, traps are assumed to accumulate over a wide region extending laterally from the gate edge towards the drain contact, whereas, under off-state stress, trap generation is supposed to take place in a narrower portion of the drain access region close to the gate edge and to be accompanied by a significant degradation of the channel transport parameters.
Investigation of High-Electric-Field Degradation Effects in AlGaN/GaN HEMTs / Faqir, Mustapha; Verzellesi, Giovanni; G., Meneghesso; E., Zanoni; Fantini, Fausto. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - STAMPA. - 55:7(2008), pp. 1592-1602. [10.1109/TED.2008.924437]
Investigation of High-Electric-Field Degradation Effects in AlGaN/GaN HEMTs
FAQIR, Mustapha;VERZELLESI, Giovanni;FANTINI, Fausto
2008
Abstract
High-electric-field degradation phenomena are investigated in GaN-capped AlGaN-GaN HEMTs by comparing experimental data with numerical device simulations. 150-hour DC stresses were carried out under power-state and off-state conditions. Degradations effects characterizing both stress experiments were: a drop in the DC drain current, the amplification of gate-lag effects, and a decrease in the reverse gate leakage current. Numerical simulations indicate that the simultaneous generation of surface (and/or barrier) traps and of buffer traps can account for all of the above degradation modes. Experiments showed also that the power-state stress induced a drop in the transconductance at high gate-source voltages only, whereas the off-state stress led to a uniform transconductance drop over the entire gate-source-voltage range. This behavior can be reproduced by simulations provided that, under power-state stress, traps are assumed to accumulate over a wide region extending laterally from the gate edge towards the drain contact, whereas, under off-state stress, trap generation is supposed to take place in a narrower portion of the drain access region close to the gate edge and to be accompanied by a significant degradation of the channel transport parameters.File | Dimensione | Formato | |
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