In this paper, we revisit Boole's expansion theorem to propose a new synthesis method for implication logic circuits based on memristors. By rewriting the sum-of-products form of Boole's expansion theorem in terms that are best suited for the implication logic, we develop a generalized rule to derive the sequence of operations needed to realize any logic function written in the classical AND-OR form. The proposed method leverages on multi-input operation, minimizing both the number of steps required to compute a given Boolean function and the number of memristors involved. Moreover, it allows using well-established methods of logic circuit optimization like binary decision diagrams, Karnaugh maps, and heuristic algorithms, that are already implemented in commercial CAD software. The proposed method allows a fair comparison between the performance of CMOS and implication logic implementations of the same logic function under the same degree of optimization, and is shown to outperform existing approaches. Possible device-circuit co-design strategies to optimize circuit performance are finally discussed.

Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication Logic With Emerging Non-Volatile Memories / Puglisi, F. M.; Zanotti, T.; Pavan, P.. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS. - ISSN 1549-8328. - 68:11(2021), pp. 4433-4443. [10.1109/TCSI.2021.3079986]

Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication Logic With Emerging Non-Volatile Memories

Puglisi F. M.;Zanotti T.;Pavan P.
2021

Abstract

In this paper, we revisit Boole's expansion theorem to propose a new synthesis method for implication logic circuits based on memristors. By rewriting the sum-of-products form of Boole's expansion theorem in terms that are best suited for the implication logic, we develop a generalized rule to derive the sequence of operations needed to realize any logic function written in the classical AND-OR form. The proposed method leverages on multi-input operation, minimizing both the number of steps required to compute a given Boolean function and the number of memristors involved. Moreover, it allows using well-established methods of logic circuit optimization like binary decision diagrams, Karnaugh maps, and heuristic algorithms, that are already implemented in commercial CAD software. The proposed method allows a fair comparison between the performance of CMOS and implication logic implementations of the same logic function under the same degree of optimization, and is shown to outperform existing approaches. Possible device-circuit co-design strategies to optimize circuit performance are finally discussed.
68
11
4433
4443
Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication Logic With Emerging Non-Volatile Memories / Puglisi, F. M.; Zanotti, T.; Pavan, P.. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS. - ISSN 1549-8328. - 68:11(2021), pp. 4433-4443. [10.1109/TCSI.2021.3079986]
Puglisi, F. M.; Zanotti, T.; Pavan, P.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11380/1248301
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