ZANOTTI, TOMMASO

ZANOTTI, TOMMASO  

Dipartimento di Ingegneria "Enzo Ferrari"  

Mostra records
Risultati 1 - 20 di 24 (tempo di esecuzione: 0.048 secondi).
Titolo Data di pubblicazione Autore(i) File
Advanced Data Encryption ​using 2D Materials 1-gen-2021 Wen, Chao; Li, Xuehua; Zanotti, Tommaso; Puglisi, Francesco Maria; Shi, Yuanyuan; Saiz, Fernan; Antidormi, Aleandro; Roche, Stephan; Zheng, Wenwen; Liang, Xianhu; Hu, Jiaxin; Duhm, Steffen; Roldan, Juan B.; Wu, Tianru; Chen, Victoria; Pop, Eric; Garrido, Blas; Zhu, Kaichen; Hui, Fei; Lanza, Mario
Circuit Reliability Analysis of In-Memory Inference in Binarized Neural Networks 1-gen-2020 Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
Circuit Reliability Analysis of RRAM-based Logic-in-Memory Crossbar Architectures Including Line Parasitic Effects, Variability, and Random Telegraph Noise 1-gen-2020 Zanotti, T.; Puglisi, F. M.; Pavan, P.
Circuit reliability of low-power rram-based logic-in-memory architectures 1-gen-2019 Zanotti, T.; Puglisi, F. M.; Pavan, P.
Circuiti innovativi ad alta efficienza energetica per l'elaborazione sicura in memoria basati su dispositivi di memoria resistivi 24-mar-2022 Zanotti, Tommaso
Comprehensive physics-based RRAM compact model including the effect of variability and multi-level random telegraph noise 1-gen-2022 Zanotti, T; Pavan, P; Puglisi, Fm
Energy-efficient non-von neumann computing architecture supporting multiple computing paradigms for logic and binarized neural networks 1-gen-2021 Zanotti, T.; Puglisi, F. M.; Pavan, P.
Low-Bit Precision Neural Network Architecture with High Immunity to Variability and Random Telegraph Noise based on Resistive Memories 1-gen-2021 Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
METODO DI LETTURA PER CIRCUITI DEL TIPO LOGIC-IN-MEMORY E RELATIVA ARCHITETTURA CIRCUITALE 12-ago-2019 Puglisi, Francesco Maria; Pavan, Paolo; Zanotti, Tommaso
Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing 1-gen-2021 Zanotti, Tommaso; Pavan, Paolo; Puglisi, Francesco Maria
Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication Logic With Emerging Non-Volatile Memories 1-gen-2021 Puglisi, F. M.; Zanotti, T.; Pavan, P.
Performances and Trade-offs of Low-Bit Precision Neural Networks based on Resistive Memories 1-gen-2021 Zanotti, T.; Pavan, P.; Puglisi, F. M.
Random Telegraph Noise in Metal-Oxide Memristors for True Random Number Generators: A Materials Study 1-gen-2021 Li, X.; Zanotti, T.; Wang, T.; Zhu, K.; Puglisi, F. M.; Lanza, M.
Reconfigurable Smart In-Memory Computing Platform Supporting Logic and Binarized Neural Networks for Low-Power Edge Devices 1-gen-2020 Zanotti, T.; Puglisi, F. M.; Pavan, P.
Reliability and Performance Analysis of Logic-in-Memory Based Binarized Neural Networks 1-gen-2021 Zanotti, T.; Puglisi, F. M.; Pavan, P.
Reliability and Prospects of Logic-in-Memory Circuits 1-gen-2022 Zanotti, T
Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays 1-gen-2020 Zanotti, T.; Zambelli, C.; Puglisi, F. M.; Milo, V.; Perez, E.; Mahadevaiah, M. K.; Ossorio, O. G.; Wenger, C.; Pavan, P.; Olivo, P.; Ielmini, D.
Reliability-Aware Design Strategies for Stateful Logic-in-Memory Architectures 1-gen-2020 Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo
SIMPLY: Design of a RRAM-Based Smart Logic-in-Memory Architecture using RRAM Compact Model 1-gen-2019 Puglisi, F. M.; Zanotti, T.; Pavan, P.
A Smart Logic-in-Memory Architecture for Low-Power non-von Neumann Computing 1-gen-2020 Zanotti, Tommaso; Puglisi, Francesco Maria; Pavan, Paolo