Logic circuits based on Resistive RAM (RRAM) devices and the material implication logic (IMPLY) are promising solutions for low-power logic-in-memory (LiM) architectures. Still, their diffusion is limited by their high design complexity resulting from device and circuit non-idealities. These non-idealities are usually overlooked in the design phase when using simplified RRAM models, thus leading to unreliable designs. In this work, we derive correct design strategies for reliability of RRAM-based LiM circuits and quantitatively evaluate circuit performances using a physics-based compact model.
Circuit reliability of low-power rram-based logic-in-memory architectures / Zanotti, T.; Puglisi, F. M.; Pavan, P.. - 2019-:(2019), pp. 1-5. (Intervento presentato al convegno 2019 IEEE International Integrated Reliability Workshop, IIRW 2019 tenutosi a usa nel 2019) [10.1109/IIRW47491.2019.8989875].