Circuit Reliability Analysis of RRAM-based Logic-in-Memory Crossbar Architectures Including Line Parasitic Effects, Variability, and Random Telegraph Noise

The Logic-in-Memory paradigm is considered a promising solution for improving the energy efficiency and computing power of architectures aimed at low power and/or data-intensive applications. Among in-memory computing enabling technologies, emerging non-volatile memories (e.g., RRAMs) are promising as they offer BEOL integration and small feature size. Several studies have shown that IMPLY architectures based on RRAM devices and the material implication logic enable the efficient computation of logic operations using the RRAM device both as storing and computing element. However, RRAM devices non-idealities introduce important circuit reliability issues, that are frequently neglected, thus undermining the circuit functionality. In this work, we use a physics-based compact model calibrated on experimental data to simulate the IMPLY operation performed on a crossbar array including line parasitic effects and RRAM devices non-idealities. We then introduce a novel smart scheme, SIMPLY, and show the circuit reliability improvement.