In this work, we introduce a new RRAM-based Smart IMPLY (SIMPLY) logic scheme with unique benefits for low-power systems and verify its feasibility and advantages by means of circuit simulations allowing appropriate device/circuit requirements co-design. Differently from previous works, we use a physics-based compact model of RRAM devices able to reproduce both the ultrafast AC and the DC behavior, accounting for the intrinsic variability of the resistive states, the occurrence of Random Telegraph Noise, and the logic state degradation. The proposed scheme strongly alleviates the issue of logic state degradation, breaks the trade-off between the choice of VSET and VCOND, and allows saving energy up to a factor of ~230 requiring minimum area overhead.

SIMPLY: Design of a RRAM-Based Smart Logic-in-Memory Architecture using RRAM Compact Model / Puglisi, F. M.; Zanotti, T.; Pavan, P.. - 2019-(2019), pp. 130-133. ((Intervento presentato al convegno 49th European Solid-State Device Research Conference, ESSDERC 2019 tenutosi a pol nel 2019 [10.1109/ESSDERC.2019.8901731].

I metadati presenti in IRIS UNIMORE sono rilasciati con licenza Creative Commons CC0 1.0 Universal, mentre i file delle pubblicazioni sono rilasciati con licenza Attribuzione 4.0 Internazionale (CC BY 4.0), salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris

Powered by IRIS-about IRIS-Utilizzo dei cookie

 Copyright © 2022