In this work, we explore the RRAM-based IMPLY logic by means of circuit simulations. Differently from previous works, we use a physics-based compact model of RRAM devices able to reproduce both the AC and the DC behavior, accounting for the intrinsic variability of the resistive states and the logic state degradation. A new implementation of a 1-bit full adder with unique properties for low-power circuits is proposed, and its performance in terms of energy consumption and execution time is evaluated by simulations. Results are compared against recent experiments, demonstrating a good agreement and indicating the direction for further improvement.
Energy-efficient logic-in-memory I-bit full adder enabled by a physics-based RRAM compact model / Puglisi, Francesco Maria; Pacchioni, Lorenzo; Zagni, Nicolo; Pavan, Paolo. - 2018-:(2018), pp. 50-53. (Intervento presentato al convegno 48th European Solid-State Device Research Conference, ESSDERC 2018 tenutosi a Dresden nel 2018) [10.1109/ESSDERC.2018.8486886].