Abstract: In this paper, we delve into one of the most relevant defects-related phenomena causing failures in the operation of modern nanoscale electron devices, namely Random Telegraph Noise (RTN). Due to its detrimental impact on devices and circuits performances, RTN mechanism must be thoroughly understood, which requires establishing a self-consistent framework encompassing automated measurement techniques, data analysis algorithms, and physics-based modeling. This platform is not only required to understand the physics of RTN-related failures, but also to enable RTN analysis as a tool to investigate device reliability. Starting from the analysis of RTN signal statistical properties, we propose a set of guidelines to perform correct RTN measurements and data analysis, in order to get reliable results that are needed for an unbiased physical interpretation. This is achieved by combining automated experiments with sophisticated data analysis, consistency check, and comprehensive physics-based simulations. RTN analysis is then applied to two different devices for logic and memory applications, respectively: FinFETs and RRAMs. Particularly, the analysis of the statistical properties of RTN simultaneously measured on the drain and on the gate current of FinFETs allows understanding the details of the defects generation during stress. The analysis of RTN measured during the read operation in RRAM devices allows understanding the physical origin of RTN in these devices and identifying the defects species involved in this phenomenon.

Random telegraph noise: Measurement, data analysis, and interpretation / Puglisi, Francesco Maria; Padovani, Andrea; Larcher, Luca; Pavan, Paolo. - 2017-:(2017), pp. 1-9. ((Intervento presentato al convegno 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017 tenutosi a Chengdu, China nel 4-7 July 2017 [10.1109/IPFA.2017.8060057].

Random telegraph noise: Measurement, data analysis, and interpretation

PUGLISI, Francesco Maria;PADOVANI, ANDREA;LARCHER, Luca;PAVAN, Paolo
2017

Abstract

Abstract: In this paper, we delve into one of the most relevant defects-related phenomena causing failures in the operation of modern nanoscale electron devices, namely Random Telegraph Noise (RTN). Due to its detrimental impact on devices and circuits performances, RTN mechanism must be thoroughly understood, which requires establishing a self-consistent framework encompassing automated measurement techniques, data analysis algorithms, and physics-based modeling. This platform is not only required to understand the physics of RTN-related failures, but also to enable RTN analysis as a tool to investigate device reliability. Starting from the analysis of RTN signal statistical properties, we propose a set of guidelines to perform correct RTN measurements and data analysis, in order to get reliable results that are needed for an unbiased physical interpretation. This is achieved by combining automated experiments with sophisticated data analysis, consistency check, and comprehensive physics-based simulations. RTN analysis is then applied to two different devices for logic and memory applications, respectively: FinFETs and RRAMs. Particularly, the analysis of the statistical properties of RTN simultaneously measured on the drain and on the gate current of FinFETs allows understanding the details of the defects generation during stress. The analysis of RTN measured during the read operation in RRAM devices allows understanding the physical origin of RTN in these devices and identifying the defects species involved in this phenomenon.
24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
Chengdu, China
4-7 July 2017
2017-
1
9
Puglisi, Francesco Maria; Padovani, Andrea; Larcher, Luca; Pavan, Paolo
Random telegraph noise: Measurement, data analysis, and interpretation / Puglisi, Francesco Maria; Padovani, Andrea; Larcher, Luca; Pavan, Paolo. - 2017-:(2017), pp. 1-9. ((Intervento presentato al convegno 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017 tenutosi a Chengdu, China nel 4-7 July 2017 [10.1109/IPFA.2017.8060057].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1148057
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