In this work, we propose for the first time a Verilog-A physics-based compact model of Random Telegraph Noise (RTN) in Resistive Random Access Memory (RRAM) devices. Starting from the physics of the RTN mechanism in both high (HRS) and low (LRS) resistive states, and combining experimental data with physics-based simulations, we develop and validate a complete compact model of RTN in RRAM devices. The model accounts for the intrinsic randomness in the number of defects contributing to the RTN and their properties. Moreover, it can be readily integrated in existing RRAM device compact models, extending their capabilities. The model is implemented in Verilog-A, and its effectiveness is demonstrated by using it to design the building block of a Truly-Random Number Generator circuit exploiting the RTN randomness as an entropy source.

A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design / Puglisi, Francesco Maria; Zagni, Nicolo'; Larcher, Luca; Pavan, Paolo. - (2017), pp. 204-207. ((Intervento presentato al convegno 47th European Solid-State Device Research Conference, ESSDERC 2017 tenutosi a Leuven (B) nel 11-14 Sept. 2017 [10.1109/ESSDERC.2017.8066627].

A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design

PUGLISI, Francesco Maria;ZAGNI, NICOLO';LARCHER, Luca;PAVAN, Paolo
2017

Abstract

In this work, we propose for the first time a Verilog-A physics-based compact model of Random Telegraph Noise (RTN) in Resistive Random Access Memory (RRAM) devices. Starting from the physics of the RTN mechanism in both high (HRS) and low (LRS) resistive states, and combining experimental data with physics-based simulations, we develop and validate a complete compact model of RTN in RRAM devices. The model accounts for the intrinsic randomness in the number of defects contributing to the RTN and their properties. Moreover, it can be readily integrated in existing RRAM device compact models, extending their capabilities. The model is implemented in Verilog-A, and its effectiveness is demonstrated by using it to design the building block of a Truly-Random Number Generator circuit exploiting the RTN randomness as an entropy source.
47th European Solid-State Device Research Conference, ESSDERC 2017
Leuven (B)
11-14 Sept. 2017
204
207
Puglisi, Francesco Maria; Zagni, Nicolo'; Larcher, Luca; Pavan, Paolo
A new verilog-A compact model of random telegraph noise in oxide-based RRAM for advanced circuit design / Puglisi, Francesco Maria; Zagni, Nicolo'; Larcher, Luca; Pavan, Paolo. - (2017), pp. 204-207. ((Intervento presentato al convegno 47th European Solid-State Device Research Conference, ESSDERC 2017 tenutosi a Leuven (B) nel 11-14 Sept. 2017 [10.1109/ESSDERC.2017.8066627].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1146582
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