MARONGIU, ANDREA

MARONGIU, ANDREA  

Dipartimento di Scienze Fisiche, Informatiche e Matematiche  

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Titolo Data di pubblicazione Autore(i) File
ADRENALINE: An OpenVX Environment to Optimize Embedded Vision Applications on Many-core Accelerators 1-gen-2015 Tagliavini, Giuseppe; Haugou, Germain; Marongiu, Andrea; Benini, Luca
Always-on motion detection with application-level error control on a near-threshold approximate computing platform 1-gen-2016 Tagliavini, Giuseppe; Marongiu, Andrea; Rossi, Davide; Benini, Luca
An energy-efficient parallel algorithm for real-time near-optimal UAV path planning 1-gen-2016 Palossi, D; Furci, M; Naldi, R; Marongiu, A; Marconi, L; Benini, L
An optimized task-based runtime system for resource-constrained parallel accelerators 1-gen-2016 Cesarini, D; Marongiu, A; Benini, L
Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology 1-gen-2008 Marongiu, Andrea; Acquaviva, Andrea; Benini, Luca; Bartolini, Andrea
Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters 1-gen-2013 Burgio, P.; Marongiu, A.; Danilo, R.; Coussy, P.; Benini, L.
Architecture support for tightly-coupled multi-core clusters with shared-memory HW accelerators 1-gen-2015 Dehyadegari, Masoud; Marongiu, Andrea; Kakoee Mohammad, Reza; Mohammadi, Siamak; Yazdani, Naser; Benini, Luca
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain 1-gen-2014 Balboni, Marco; Obon Marta, Ortin; Capotondi, Alessandro; Tatenguem Hervé, Fankem; Ghiribaldi, Alberto; Ramini, Luca; Viñal, Victor; Marongiu, Andrea; Bertozzi, Davide
Automatic application partitioning on FPGA/CPU systems based on detailed low-level information 1-gen-2006 Busonera, Giovanni; Marongiu, Andrea; Carta, Salvatore; Raffo, Luigi
Combining PREM compilation and ILP scheduling for high-performance and predictable MPSoC execution 1-gen-2018 Matějka, Joel; Hanzálek, Zdeněk; Forsberg, Björn; Benini, Luca; Sojka, Michal; Marongiu, Andrea
Combining PREM compilation and static scheduling for high-performance and predictable MPSoC execution 1-gen-2019 Matejka, J.; Forsberg, B.; Sojka, M.; Sucha, P.; Benini, L.; Marongiu, A.; Hanzalek, Z.
Controlling NUMA effects in embedded manycore applications with lightweight nested parallelism support 1-gen-2016 Marongiu, A; Capotondi, A; Benini, L
Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA 1-gen-2019 Tagliavini, G.; MacH, S.; Rossi, D.; Marongiu, A.; Benini, L.
Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs 1-gen-2012 Abellan, J. L.; Fernandez, J.; Acacio, M. E.; Bertozzi, Davide; Bortolotti, Daniele; Marongiu, Andrea; Benini, Luca
Dissecting the CUDA scheduling hierarchy: A Performance and Predictability Perspective 1-gen-2020 Olmedo, I. S.; Capodieci, N.; Martinez, J. L.; Marongiu, A.; Bertogna, M.
Edge-TM: Exploiting transactional memory for error tolerance and energy efficiency 1-gen-2017 Papagiannopoulou, Dimitra; Marongiu, Andrea; Moreshet, Tali; Herlihy, Maurice; Bahar, R. Iris
Efficient OpenMP data mapping for multicore platforms with vertically stacked memory 1-gen-2010 Marongiu, Andrea; Ruggiero, M.; Benini, Luca
Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy 1-gen-2009 Marongiu, A.; Benini, L.
Efficient virtual memory sharing via on-accelerator page table walking in heterogeneous embedded SoCs 1-gen-2017 Vogel, Pirmin; Kurth, Andreas; Weinbuch, Johannes; Marongiu, Andrea; Benini, Luca
Embedded operating systems 1-gen-2018 Scordino, C.; Guidieri, E.; Morelli, B.; Marongiu, A.; Tagliavini, G.; Gai, P.