We propose a tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and accuracy-reconfigurable floating-point units (FPUs). The resilient shared-FPUs dynamically characterize FP pipeline vulnerability (FPV) and expose it as metadata to a software scheduler for reducing the cost of error correction. To further reduce this cost, our programming and runtime environment also supports controlled approximate computation through a combination of design-time and runtime techniques. We provide OpenMP extensions (as custom directives) for FP computations to specify parts of a program that can be executed approximately. We use a profiling technique to identify tolerable error significance and error rate thresholds in error-tolerant image processing applications. This information guides an application-driven hardware FPU synthesis and optimization design flow to generate efficient FPUs. At runtime, the scheduler utilizes FPV metadata and promotes FPUs to accurate mode, or demotes them to approximate mode depending upon the code region requirements. We demonstrate the effectiveness of our approach (in terms of energy savings) on a 16-core tightly-coupled cluster with eight shared-FPUs for both error-tolerant and general-purpose error-intolerant applications.

A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters / Rahimi, Abbas; Marongiu, Andrea; Gupta, Rajesh K.; Benini, Luca. - STAMPA. - (2013), pp. 1-10. (Intervento presentato al convegno 11th ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013 tenutosi a Montreal, QC; Canada nel Sept. 29 2013-Oct. 4 2013) [10.1109/CODES-ISSS.2013.6659022].

A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters

Andrea Marongiu;
2013

Abstract

We propose a tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and accuracy-reconfigurable floating-point units (FPUs). The resilient shared-FPUs dynamically characterize FP pipeline vulnerability (FPV) and expose it as metadata to a software scheduler for reducing the cost of error correction. To further reduce this cost, our programming and runtime environment also supports controlled approximate computation through a combination of design-time and runtime techniques. We provide OpenMP extensions (as custom directives) for FP computations to specify parts of a program that can be executed approximately. We use a profiling technique to identify tolerable error significance and error rate thresholds in error-tolerant image processing applications. This information guides an application-driven hardware FPU synthesis and optimization design flow to generate efficient FPUs. At runtime, the scheduler utilizes FPV metadata and promotes FPUs to accurate mode, or demotes them to approximate mode depending upon the code region requirements. We demonstrate the effectiveness of our approach (in terms of energy savings) on a 16-core tightly-coupled cluster with eight shared-FPUs for both error-tolerant and general-purpose error-intolerant applications.
2013
11th ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013
Montreal, QC; Canada
Sept. 29 2013-Oct. 4 2013
1
10
Rahimi, Abbas; Marongiu, Andrea; Gupta, Rajesh K.; Benini, Luca
A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters / Rahimi, Abbas; Marongiu, Andrea; Gupta, Rajesh K.; Benini, Luca. - STAMPA. - (2013), pp. 1-10. (Intervento presentato al convegno 11th ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013 tenutosi a Montreal, QC; Canada nel Sept. 29 2013-Oct. 4 2013) [10.1109/CODES-ISSS.2013.6659022].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1171902
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