Modern cyber-physical systems (CPS) are increasingly adopting heterogeneous systems-on-chip (HeSoCs) as a computing platform to satisfy the demands of their sophisticated workloads. FPGA-based HeSoCs can reach high performance and energy efficiency at the cost of increased design complexity. High-Level Synthesis (HLS) can ease IP design, but automated tools still lack the maturity to efficiently and easily tackle system-level integration of the many hardware and software blocks included in a modern CPS. We present an innovative hardware overlay offering plug-and-play integration of HLS-compiled or handcrafted acceleration IPs thanks to a customizable wrapper attached to the overlay interconnect and providing shared-memory communication to the overlay cores. The latter are based on the open RISC-V ISA and offer simplified software management of the acceleration IP. Deploying the proposed overlay on a Xilinx ZU9EG shows ≈ 20% LUT usage and ≈ 4× speedup compared to program execution on the ARM host core.

A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment / Bellocchi, Gianluca; Capotondi, Alessandro; Conti, Francesco; Marongiu, Andrea. - (2021), pp. 9-17. ((Intervento presentato al convegno 24th Euromicro Conference on Digital System Design, DSD 2021 tenutosi a Palermo nel 1-3 Settembre 2021 [10.1109/DSD53832.2021.00011].

A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment

Bellocchi, Gianluca;Capotondi, Alessandro
;
Marongiu, Andrea
2021

Abstract

Modern cyber-physical systems (CPS) are increasingly adopting heterogeneous systems-on-chip (HeSoCs) as a computing platform to satisfy the demands of their sophisticated workloads. FPGA-based HeSoCs can reach high performance and energy efficiency at the cost of increased design complexity. High-Level Synthesis (HLS) can ease IP design, but automated tools still lack the maturity to efficiently and easily tackle system-level integration of the many hardware and software blocks included in a modern CPS. We present an innovative hardware overlay offering plug-and-play integration of HLS-compiled or handcrafted acceleration IPs thanks to a customizable wrapper attached to the overlay interconnect and providing shared-memory communication to the overlay cores. The latter are based on the open RISC-V ISA and offer simplified software management of the acceleration IP. Deploying the proposed overlay on a Xilinx ZU9EG shows ≈ 20% LUT usage and ≈ 4× speedup compared to program execution on the ARM host core.
24th Euromicro Conference on Digital System Design, DSD 2021
Palermo
1-3 Settembre 2021
9
17
Bellocchi, Gianluca; Capotondi, Alessandro; Conti, Francesco; Marongiu, Andrea
A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment / Bellocchi, Gianluca; Capotondi, Alessandro; Conti, Francesco; Marongiu, Andrea. - (2021), pp. 9-17. ((Intervento presentato al convegno 24th Euromicro Conference on Digital System Design, DSD 2021 tenutosi a Palermo nel 1-3 Settembre 2021 [10.1109/DSD53832.2021.00011].
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11380/1255170
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