We present an analytical model of TANOS program/erase transients that can be used to implement a compact SPICE-like model of these memory devices. Simulation results obtained from a physics-based TANOS model are used to derive simple analytical formulas relating the program/erase currents and the centroid of the trapped charge distribution to operating conditions and stack composition. The model allows reproducing with a good agreement the experimental program/erase transients, thus providing a valuable tool for IC designers to optimize TANOS memory circuits, especially in the framework of multi-level applications.
Compact modeling of TANOS program/erase operations for SPICE-like circuit simulations / Padovani, Andrea; Larcher, Luca; Pavan, Paolo. - In: MICROELECTRONICS JOURNAL. - ISSN 0959-8324. - ELETTRONICO. - 44:1(2013), pp. 50-57. [10.1016/j.mejo.2011.07.017]
Compact modeling of TANOS program/erase operations for SPICE-like circuit simulations
PADOVANI, ANDREA;LARCHER, Luca;PAVAN, Paolo
2013
Abstract
We present an analytical model of TANOS program/erase transients that can be used to implement a compact SPICE-like model of these memory devices. Simulation results obtained from a physics-based TANOS model are used to derive simple analytical formulas relating the program/erase currents and the centroid of the trapped charge distribution to operating conditions and stack composition. The model allows reproducing with a good agreement the experimental program/erase transients, thus providing a valuable tool for IC designers to optimize TANOS memory circuits, especially in the framework of multi-level applications.
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