In this paper, we will review the modeling strategies for standard and advanced Flash memory devices based on Floating Gate devices developed by our research group in the last ten years. We will show a complete compact model that includes program/erase and leakage currents that can be used to simulate memory cells in both DC (read operation) and transient conditions (Program/Erase). The same model can be used also for reliability simulations by providing good descriptions of the degradation mechanisms. We will also show the extended model for circuit simulation of NAND strings, modified to account for capacitive coupling effects. Finally, we will show how the same framework can be used to develop a compact model for operations of advanced planar charge-trapping memory devices.
Modeling strategies for flash memory devices / Padovani, Andrea; Larcher, Luca; Pavan, Paolo. - STAMPA. - 2:(2011), pp. 762-767. (Intervento presentato al convegno Nanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011 tenutosi a Boston (MA) nel 13 giugno 2011 - 16 giugno 2011).