The understanding of the physical mechanisms responsible of charge transport and degradation in high-k stacks is fundamental for the optimization of advanced logic (MOSFETs) and memory (RRAM, DRAM) devices. In this paper, we present a comprehensive physical model describing the charge transport and the degradation/breakdown processes in the HfO2 layer. This model allows gaining quantitative insights into the physics governing leakage current and degradation processes in HfO2 stacks, reproducing gate current and TDDB statistics
Physical modeling of charge transport and degradation in HfO 2 stacks for logic device and memory applications / Larcher, Luca; Padovani, Andrea; Vandelli, Luca; G., Bersuker. - In: ECS TRANSACTIONS. - ISSN 1938-5862. - STAMPA. - 37:1(2011), pp. 189-197. ((Intervento presentato al convegno 3rd International Conference on Semiconductor Technology for Ultra Large Integrated Circuits and Thin Film Transistors, ULSIC vs. TFT III tenutosi a Hong Kong, chn nel 2011 [10.1149/1.3600739].
Physical modeling of charge transport and degradation in HfO 2 stacks for logic device and memory applications
LARCHER, Luca;PADOVANI, ANDREA;VANDELLI, LUCA;
2011
Abstract
The understanding of the physical mechanisms responsible of charge transport and degradation in high-k stacks is fundamental for the optimization of advanced logic (MOSFETs) and memory (RRAM, DRAM) devices. In this paper, we present a comprehensive physical model describing the charge transport and the degradation/breakdown processes in the HfO2 layer. This model allows gaining quantitative insights into the physics governing leakage current and degradation processes in HfO2 stacks, reproducing gate current and TDDB statistics
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