We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-kappa dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-kappapsilas traps on leakage current distribution for flash memory applications. We demonstrate that the high defectiveness typical of high-k materials strongly reduces the potential improvement due to the introduction of band-gap engineered high-kappa tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-kappa tunnel stacks and to improve technology reliability issues related to flash memory applications.

Statistical modeling of leakage currents through SiO2/high-k dielectric stacks for non-volatile memory applications / Padovani, Andrea; Larcher, Luca; S., Verma; Pavan, Paolo; P., Majhi; P., Kapur; K., Parat; G., Bersuker; K., Saraswat. - STAMPA. - (2008), pp. 616-620. ((Intervento presentato al convegno Reliability Physics Symposium, 2008. IRPS 2008. IEEE International tenutosi a Phoenix (UAZ, SA) nel April 27 2008-May 1 2008.

Statistical modeling of leakage currents through SiO2/high-k dielectric stacks for non-volatile memory applications

PADOVANI, ANDREA;LARCHER, Luca;PAVAN, Paolo;
2008

Abstract

We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-kappa dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-kappapsilas traps on leakage current distribution for flash memory applications. We demonstrate that the high defectiveness typical of high-k materials strongly reduces the potential improvement due to the introduction of band-gap engineered high-kappa tunnel dielectric stacks. In this regard, the simulator is a useful tool to optimize high-kappa tunnel stacks and to improve technology reliability issues related to flash memory applications.
Reliability Physics Symposium, 2008. IRPS 2008. IEEE International
Phoenix (UAZ, SA)
April 27 2008-May 1 2008
616
620
Padovani, Andrea; Larcher, Luca; S., Verma; Pavan, Paolo; P., Majhi; P., Kapur; K., Parat; G., Bersuker; K., Saraswat
Statistical modeling of leakage currents through SiO2/high-k dielectric stacks for non-volatile memory applications / Padovani, Andrea; Larcher, Luca; S., Verma; Pavan, Paolo; P., Majhi; P., Kapur; K., Parat; G., Bersuker; K., Saraswat. - STAMPA. - (2008), pp. 616-620. ((Intervento presentato al convegno Reliability Physics Symposium, 2008. IRPS 2008. IEEE International tenutosi a Phoenix (UAZ, SA) nel April 27 2008-May 1 2008.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11380/590231
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