Two-dimensional device simulations are adopted as a tool to characterize deep levels in 6H-SiC, buried gate, n-channel JFETs. Deep levels can be detected by means of Deep Level Transient Spectroscopy (DLTS) or transconductance frequency dispersion measurements. Subsequent simulation of the drain-current transients following the application of a gate-source voltage step allows the energetic and spatial position of the different deep levels to be inferred.

Deep-level characterization in 6H-SiC JFETs by means of two-dimensional device simulations / Verzellesi, Giovanni; G., Meneghesso; Mazzanti, Andrea; Canali, Claudio; E., Zanoni. - STAMPA. - (2002). ((Intervento presentato al convegno Workshop on Physical Simulation of Semiconductor Devices (PSSD) tenutosi a Leeds (UK) nel Mar. 2002.

Deep-level characterization in 6H-SiC JFETs by means of two-dimensional device simulations

VERZELLESI, Giovanni;MAZZANTI, Andrea;CANALI, Claudio;
2002

Abstract

Two-dimensional device simulations are adopted as a tool to characterize deep levels in 6H-SiC, buried gate, n-channel JFETs. Deep levels can be detected by means of Deep Level Transient Spectroscopy (DLTS) or transconductance frequency dispersion measurements. Subsequent simulation of the drain-current transients following the application of a gate-source voltage step allows the energetic and spatial position of the different deep levels to be inferred.
Workshop on Physical Simulation of Semiconductor Devices (PSSD)
Leeds (UK)
Mar. 2002
Verzellesi, Giovanni; G., Meneghesso; Mazzanti, Andrea; Canali, Claudio; E., Zanoni
Deep-level characterization in 6H-SiC JFETs by means of two-dimensional device simulations / Verzellesi, Giovanni; G., Meneghesso; Mazzanti, Andrea; Canali, Claudio; E., Zanoni. - STAMPA. - (2002). ((Intervento presentato al convegno Workshop on Physical Simulation of Semiconductor Devices (PSSD) tenutosi a Leeds (UK) nel Mar. 2002.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11380/467027
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