Experimental/numerical investigation of the physical mechanisms behind high-field degradation of power HFETs and their implications on device design

In a previous paper we showed how simple drift-diffusion simulations backed up the hypothesis of electron trapping at the device surface between gate and drain as a mechanism able to consistently explain all of the experimentally observed degradation modes following a high-field (hot carrier) stress. This paper expands on such previous findings by showing: (i) simulation results of HFETs with different recess geometries, and their implications on breakdown voltage and reliability; (ii) a detailed experimental and numerical investigation of surface trapping effects such as gate lag, transconductance frequency dispersion, and drain current kink, and their relationship with device degradation.