Optimized Bulk-Linearized Pseudo-Resistor for Subthreshold Circuits

The bulk-linearization technique extends the linear region of a metal oxide semiconductor field effect transistor (MOSFET), even when operating in subthreshold region. This capability is particularly useful for the design of energy efficient pseudo-resistors, which are essential building blocks for ultra-low power integrated circuit design. In this paper we implement and experimentally validate a design optimization strategy of the bulk-linearization technique for the design of pseudo-resistors. We show that the optimization strategy enables reducing both the offset and the power consumption, without significant alteration of the area occupation. The validated strategy is then applied in the design of a CMOS current-mode logarithmic amplifier with transistors operating in subthreshold. Measurement results demonstrate the validity of the approach in different operating conditions, also showing best-in-class performance in terms of area occupation and power consumption.