Enhanced Memory Performance in Ferroelectric NAND Applications: The Role of Tunnel Dielectric Position for Robust 10-Year Retention

We report a comprehensive study on memory window (MW) enhancement and retention loss (RL) in ferroelectric (FE) field effect transistors for NAND applications with a dielectric layer inserted within the FE film (next to the gate ‒ GBL devices ‒ or in the middle of the FE layer ‒ TDL devices). Using a temperature-dependent modeling framework, we show that MW and RL properties are controlled respectively by carriers trapping into defects at the dielectric-FE interface and by its fragile balance with FE depolarization. While MW enhancement is achieved whenever the inserted dielectric layer is present, a robust retention is obtained only in TDL FEFETs, thanks to a stabilization of the trapped charge preventing FE depolarization. Simulation results clearly demonstrate that the fragile balance between above phenomena is ultimately controlled by the position of the dielectric layer, which determines i) the field redistribution within the stack, ii) the magnitude of charge de-trapping, and iii) the magnitude of the depolarization field. Our results provide critical guidelines for the improvement of FE 3D-NAND reliability.