Artificial intelligence (AI) is changing the way computing is performed to cope with real-world, ill-defined tasks for which traditional algorithms fail. AI requires significant memory access, thus running into the von Neumann bottleneck when implemented in standard computing platforms. In this respect, low-latency energy-efficient in-memory computing can be achieved by exploiting emerging memristive devices, given their ability to emulate synaptic plasticity, which provides a path to design large-scale brain-inspired spiking neural networks (SNNs). Several plasticity rules have been described in the brain and their coexistence in the same network largely expands the computational capabilities of a given circuit. In this work, starting from the electrical characterization and modeling of the memristor device, we propose a neuro-synaptic architecture that co-integrates in a unique platform with a single type of synaptic device to implement two distinct learning rules, namely, the spike-timing-dependent plasticity (STDP) and the Bienenstock-Cooper-Munro (BCM). This architecture, by exploiting the aforementioned learning rules, successfully addressed two different tasks of unsupervised learning.

A Hybrid CMOS-Memristor Spiking Neural Network Supporting Multiple Learning Rules / Florini, Davide; Gandolfi, Daniela; Mapelli, Jonathan; Benatti, Lorenzo; Pavan, Paolo; Puglisi, Francesco Maria. - In: IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS. - ISSN 2162-237X. - PP:(2022), pp. 1-13. [10.1109/TNNLS.2022.3202501]

A Hybrid CMOS-Memristor Spiking Neural Network Supporting Multiple Learning Rules

Florini, Davide;Gandolfi, Daniela;Mapelli, Jonathan;Benatti, Lorenzo;Pavan, Paolo;Puglisi, Francesco Maria
2022-01-01

Abstract

Artificial intelligence (AI) is changing the way computing is performed to cope with real-world, ill-defined tasks for which traditional algorithms fail. AI requires significant memory access, thus running into the von Neumann bottleneck when implemented in standard computing platforms. In this respect, low-latency energy-efficient in-memory computing can be achieved by exploiting emerging memristive devices, given their ability to emulate synaptic plasticity, which provides a path to design large-scale brain-inspired spiking neural networks (SNNs). Several plasticity rules have been described in the brain and their coexistence in the same network largely expands the computational capabilities of a given circuit. In this work, starting from the electrical characterization and modeling of the memristor device, we propose a neuro-synaptic architecture that co-integrates in a unique platform with a single type of synaptic device to implement two distinct learning rules, namely, the spike-timing-dependent plasticity (STDP) and the Bienenstock-Cooper-Munro (BCM). This architecture, by exploiting the aforementioned learning rules, successfully addressed two different tasks of unsupervised learning.
PP
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13
A Hybrid CMOS-Memristor Spiking Neural Network Supporting Multiple Learning Rules / Florini, Davide; Gandolfi, Daniela; Mapelli, Jonathan; Benatti, Lorenzo; Pavan, Paolo; Puglisi, Francesco Maria. - In: IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS. - ISSN 2162-237X. - PP:(2022), pp. 1-13. [10.1109/TNNLS.2022.3202501]
Florini, Davide; Gandolfi, Daniela; Mapelli, Jonathan; Benatti, Lorenzo; Pavan, Paolo; Puglisi, Francesco Maria
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1294204
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