We derive a complete set of expressions for the MOSFET gate and drain power spectral densities due to elastic and inelastic trapping/detrapping of channel carriers into the gate dielectric. Our calculations explain trapping/detrapping noise (TDN) in various FET operating regions and highlight trap's position-dependent terms, often neglected in the literature, which are instead important for devices with thin gate dielectrics. Furthermore, we show that TDN has a contribution to the gate current noise, correlated with the drain current fluctuations and we highlight the role of the transfer function between channel charge fluctuations and drain current on the noise characteristics. The model expressions are carefully validated by comparison with 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures (bulk, fully depleted-silicon-on-insulator (FD-SOI), FinFET), channel, and gate materials. Besides shedding new light on TDN, the results could enable trap density extraction from experimental samples with improved accuracy and pave the way to complete and accurate compact models for TDN in MOSFETs.

A Comprehensive Gate and Drain Trapping/Detrapping Noise Model and Its Implications for Thin-Dielectric MOSFETs / Asanovski, R.; Palestri, P.; Caruso, E.; Selmi, L.. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - 68:10(2021), pp. 4826-4833. [10.1109/TED.2021.3104790]

A Comprehensive Gate and Drain Trapping/Detrapping Noise Model and Its Implications for Thin-Dielectric MOSFETs

Asanovski R.
;
Selmi L.
2021

Abstract

We derive a complete set of expressions for the MOSFET gate and drain power spectral densities due to elastic and inelastic trapping/detrapping of channel carriers into the gate dielectric. Our calculations explain trapping/detrapping noise (TDN) in various FET operating regions and highlight trap's position-dependent terms, often neglected in the literature, which are instead important for devices with thin gate dielectrics. Furthermore, we show that TDN has a contribution to the gate current noise, correlated with the drain current fluctuations and we highlight the role of the transfer function between channel charge fluctuations and drain current on the noise characteristics. The model expressions are carefully validated by comparison with 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures (bulk, fully depleted-silicon-on-insulator (FD-SOI), FinFET), channel, and gate materials. Besides shedding new light on TDN, the results could enable trap density extraction from experimental samples with improved accuracy and pave the way to complete and accurate compact models for TDN in MOSFETs.
20-ago-2021
68
10
4826
4833
A Comprehensive Gate and Drain Trapping/Detrapping Noise Model and Its Implications for Thin-Dielectric MOSFETs / Asanovski, R.; Palestri, P.; Caruso, E.; Selmi, L.. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - 68:10(2021), pp. 4826-4833. [10.1109/TED.2021.3104790]
Asanovski, R.; Palestri, P.; Caruso, E.; Selmi, L.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1253495
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