Capacitance-voltage (C-V) measurement and analysis is highly useful for determining important information about MOS gate stacks. Parameters such as the equivalent oxide thickness (EOT), substrate doping density, flatband voltage, fixed oxide charge, density of interface traps (Dit), and effective gate work function can all be extracted from experimental C-V curves. However, to extract these gate-stack parameters accurately, the correct models must be utilized. In Part I, we described the modeling and implementation of a C-V code that can be used for alternative channel semiconductors in conjunction with high-k gate dielectrics and metal gates. Importantly, this new code (CV ACE) includes the effects of nonparabolic bands and quantum capacitance, enabling accurate models to be applied to experimental C-V curves. In this paper, we demonstrate the capabilities of this new code to extract accurate parameters, including EOT and Dit profiles from experimental high-k on Ge and In0.53Ga0.47As gate stacks.
Comprehensive Capacitance-Voltage Simulation and Extraction Tool Including Quantum Effects for High-k on SixGe1-x and InxGa1-xAs: Part II-Fits and Extraction from Experimental Data / Anwar, Sarkar R. M.; Vandenberghe, William G.; Bersuker, Gennadi; Veksler, Dmitry; Verzellesi, Giovanni; Morassi, Luca; Galatage, Rohit V.; Jha, Sumit; Buie, Creighton; Barton, Adam T.; Vogel, Eric M.; Hinkle, Christopher L.. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - 64:9(2017), pp. 3794-3801. [10.1109/TED.2017.2725741]