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Mostrati risultati da 1 a 20 di 27
Titolo Data di pubblicazione Autore(i) File
Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP 1-gen-2013 Marongiu, Andrea; Capotondi, Alessandro; Giuseppe, Tagliavini; Luca, Benini
Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain 1-gen-2014 Balboni, Marco; Obon Marta, Ortin; Capotondi, Alessandro; Tatenguem Hervé, Fankem; Ghiribaldi, Alberto; Ramini, Luca; Viñal, Victor; Marongiu, Andrea; Bertozzi, Davide
Simplifying Many-Core-Based Heterogeneous SoC Programming with Offload Directives 1-gen-2015 Marongiu, Andrea; Capotondi, Alessandro; Tagliavini, Giuseppe; Benini, Luca
Runtime Support for Multiple Offload-Based Programming Models on Embedded Manycore Accelerators 1-gen-2015 Capotondi, Alessandro; Haugou, Germain; Marongiu, Andrea; Benini, Luca
Enabling Scalable and Fine-Grained Nested Parallelism on Embedded Many-cores 1-gen-2015 Capotondi, Alessandro; Marongiu, Andrea; Benini, Luca
PULP: A parallel ultra low power platform for next generation IoT applications 1-gen-2016 Rossi, Davide; Conti, Francesco; Marongiu, Andrea; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Tagliavini, Giuseppe; Capotondi, Alessandro; Flatresse, Philippe; Benini, Luca
On the effectiveness of OpenMP teams for cluster-based many-core accelerators 1-gen-2016 Capotondi, Alessandro; Marongiu, Andrea
Controlling NUMA effects in embedded manycore applications with lightweight nested parallelism support 1-gen-2016 Marongiu, A; Capotondi, A; Benini, L
Enabling zero-copy OpenMP ofloading on the PULP many-core accelerator 1-gen-2017 Capotondi, Alessandro; Marongiu, Andrea
Hero: An open-source research platform for HW/SW exploration of heterogeneous manycore systems 1-gen-2018 Kurth, A.; Capotondi, Alessandro; Vogel, P.; Benini, L.; Marongiu, A.
Neuraghe: Exploiting CPU-FPGA synergies for efficient and flexible CNN inference acceleration on zynQ SoCs 1-gen-2018 Meloni, P.; Capotondi, A.; Deriu, G.; Brian, M.; Conti, F.; Rossi, D.; Raffo, L.; Benini, L.
The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores 1-gen-2018 Loi, Igor; Capotondi, Alessandro; Rossi, Davide; Marongiu, Andrea; Benini, Luca
Work-in-Progress: Quantized NNs as the Definitive solution for inference on low-power ARM MCUs? 1-gen-2018 Rusci, M.; Capotondi, A.; Conti, F.; Benini, L.
Runtime Support for Multiple Offload-Based Programming Models on Clustered Manycore Accelerators 1-gen-2018 Capotondi, A; Marongiu, A; Benini, L
Leveraging Automated Mixed-Low-Precision Quantization for Tiny Edge Microcontrollers 1-gen-2020 Rusci, M.; Fariselli, M.; Capotondi, A.; Benini, L.
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge 1-gen-2020 Meloni, P.; Loi, D.; Deriu, G.; Carreras, M.; Conti, F.; Capotondi, A.; Rossi, D.
Mixed-data-model heterogeneous compilation and OpenMP offloading 1-gen-2020 Kurth, A.; Wolters, K.; Forsberg, B.; Capotondi, A.; Marongiu, A.; Grosser, T.; Benini, L.
Memory-Latency-Accuracy Trade-Offs for Continual Learning on a RISC-V Extreme-Edge Node 1-gen-2020 Ravaglia, L.; Rusci, M.; Capotondi, A.; Conti, F.; Pellegrini, L.; Lomonaco, V.; Maltoni, D.; Benini, L.
CMix-NN: Mixed Low-Precision CNN Library for Memory-Constrained Edge Devices 1-gen-2020 Capotondi, A.; Rusci, M.; Fariselli, M.; Benini, L.
A Systematic Assessment of Embedded Neural Networks for Object Detection 1-gen-2020 Verucchi, M.; Brilli, G.; Sapienza, D.; Verasani, M.; Arena, M.; Gatti, F.; Capotondi, A.; Cavicchioli, R.; Bertogna, M.; Solieri, M.
Mostrati risultati da 1 a 20 di 27
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