High performance and extreme energy efficiency are strong requirements for a fast-growing number of edge-node Internet of Things (IoT) applications. While traditional Ultra-Low-Power designs rely on single-core micro-controllers (MCU), a new generation of architectures leveraging fully programmable tightly-coupled clusters of near-threshold processors is emerging, joining the performance gain of parallel execution over multiple cores with the energy efficiency of low-voltage operation. In this work we tackle one of the most critical energy-efficiency bottlenecks for these architectures: instruction memory hierarchy. Exploiting the instruction locality typical of data-parallel applications, we explore two different shared instruction cache architectures, based on energy-efficient latch-based memory banks: one leveraging a crossbar between processors and single-port banks (SP), and one leveraging banks with multiple read ports (MP). We evaluate the proposed architectures on a set of signal processing applications with different executable sizes and working-sets. The results show that the shared cache architectures are able to efficiently execute a much wider set of applications (including those featuring large memory footprint and irregular access patterns) with a much smaller area and with much better energy efficiency with respect to the private cache. The multi-port cache is suitable for sizes up to a few kB, improving performance by up to 40%, energy efficiency by up to 20%, and energy × area efficiency by up to 30% with respect to the private cache. The single-port solution is more suitable for larger cache sizes (up to 16 kB), providing up to 20% better energy × area efficiency than the multi-port, and up to 30% better energy efficiency than private cache.
|Data di pubblicazione:||2018|
|Titolo:||The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores|
|Autore/i:||Loi, Igor; Capotondi, Alessandro; Rossi, Davide; Marongiu, Andrea; Benini, Luca|
|Digital Object Identifier (DOI):||10.1109/TMSCS.2017.2769046|
|Codice identificativo ISI:||WOS:000435509300002|
|Codice identificativo Scopus:||2-s2.0-85032836236|
|Citazione:||The Quest for Energy-Efficient I$ Design in Ultra-Low-Power Clustered Many-Cores / Loi, Igor; Capotondi, Alessandro; Rossi, Davide; Marongiu, Andrea; Benini, Luca. - In: IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS. - ISSN 2332-7766. - ELETTRONICO. - 4:2(2018), pp. 99-112.|
|Tipologia||Articolo su rivista|
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