Heterogeneous systems on chip (HeSoCs) co-integrate a high-performance multicore host processor with programmable manycore accelerators (PMCAs) to combine “standard platform” software support (e.g. the Linux OS) with energy-efficient, domain-specific, highly parallel processing capabilities. In this work, we present HERO, a HeSoC platform that tackles this challenge in a novel way. HERO’s host processor is an industry-standard ARM Cortex-A multicore complex, while its PMCA is a scalable, silicon-proven, open-source many-core processing engine, based on the extensible, open RISC-V ISA. We evaluate a prototype implementation of HERO, where the PMCA implemented on an FPGA fabric is coupled with a hard ARM Cortex-A host processor, and show that the run time overhead compared to manually written PMCA code operating on private physical memory is lower than 10 % for pivotal benchmarks and operating conditions.

Hero: An open-source research platform for HW/SW exploration of heterogeneous manycore systems / Kurth, A.; Capotondi, Alessandro; Vogel, P.; Benini, L.; Marongiu, A.. - (2018), pp. 1-6. ((Intervento presentato al convegno 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE 2018 - A Workshop part of PACT 2018 Conference tenutosi a cyp nel 2018 [10.1145/3295816.3295821].

Hero: An open-source research platform for HW/SW exploration of heterogeneous manycore systems

CAPOTONDI, ALESSANDRO;Marongiu A.
2018

Abstract

Heterogeneous systems on chip (HeSoCs) co-integrate a high-performance multicore host processor with programmable manycore accelerators (PMCAs) to combine “standard platform” software support (e.g. the Linux OS) with energy-efficient, domain-specific, highly parallel processing capabilities. In this work, we present HERO, a HeSoC platform that tackles this challenge in a novel way. HERO’s host processor is an industry-standard ARM Cortex-A multicore complex, while its PMCA is a scalable, silicon-proven, open-source many-core processing engine, based on the extensible, open RISC-V ISA. We evaluate a prototype implementation of HERO, where the PMCA implemented on an FPGA fabric is coupled with a hard ARM Cortex-A host processor, and show that the run time overhead compared to manually written PMCA code operating on private physical memory is lower than 10 % for pivotal benchmarks and operating conditions.
2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE 2018 - A Workshop part of PACT 2018 Conference
cyp
2018
1
6
Kurth, A.; Capotondi, Alessandro; Vogel, P.; Benini, L.; Marongiu, A.
Hero: An open-source research platform for HW/SW exploration of heterogeneous manycore systems / Kurth, A.; Capotondi, Alessandro; Vogel, P.; Benini, L.; Marongiu, A.. - (2018), pp. 1-6. ((Intervento presentato al convegno 2nd Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, ANDARE 2018 - A Workshop part of PACT 2018 Conference tenutosi a cyp nel 2018 [10.1145/3295816.3295821].
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11380/1179002
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