In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10-15 um in both coordinates, low material budget <1% Xo, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.
Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker / G., Rizzo; D., Comott; M., Manghisoni; V., Re; G., Traversi; L., Fabbri; A., Gabrielli; F., Giorgi; G., Pellegrini; C., Sbarra; N., Semprini Cesari; S., Valentinetti; M., Villa; A., Zoccoli; A., Berra; D., Lietti; M., Prest; A., Bevan; F., Wilson; G., Beck; J., Morris; F., Gannaway; R., Cenci; L., Bombelli; M., Citterio; S., Coelli; C., Fiorini; V., Liberali; M., Monti; B., Nasri; N., Neri; F., Palombo; A., Stabile; G., Balestri; G., Batignani; A., Bernardelli; S., Bettarini; F., Bosi; G., Casarosa; M., Ceccanti; F., Forti; M. A., Giorgi; A., Lusiani; P., Mammini; F., Morsani; B., Oberhof; E., Paoloni; A., Perez; G., Petragnani; A., Profeti; A., Soldani; J., Walsh; M., Chrzaszcz; L., Gaioni; A., Manazza; E., Quartieri; L., Ratti; S., Zucca; G., Alampi; G., Cotto; D., Gamba; S., Zambito; G. F., Dalla Betta; G., Fontana; L., Pancheri; M., Povoli; Verzellesi, Giovanni; M., Bomben; L., Bosisio; P., Cristaudo; L., Lanceri; B., Liberti; I., Rashevskaya; C., Stella; L., Vitale. - In: NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH. SECTION A, ACCELERATORS, SPECTROMETERS, DETECTORS AND ASSOCIATED EQUIPMENT. - ISSN 0168-9002. - STAMPA. - 718:(2013), pp. 283-287. [10.1016/j.nima.2012.10.084]
Recent developments on CMOS MAPS for the SuperB Silicon Vertex Tracker
VERZELLESI, Giovanni;
2013
Abstract
In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10-15 um in both coordinates, low material budget <1% Xo, and the ability to withstand a background hit rate of several tens of MHz/cm2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.
Pubblicazioni consigliate
I metadati presenti in IRIS UNIMORE sono rilasciati con licenza Creative Commons CC0 1.0 Universal, mentre i file delle pubblicazioni sono rilasciati con licenza Attribuzione 4.0 Internazionale (CC BY 4.0), salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris
