This paper describes the design and development of a Veiling Luminance estimation system based on the use of a CMOS image sensor, fully implemented on FPGA. The system is composed of the CMOS Image sensor, FPGA, DDR SDRAM, USB controller and SPI (Serial Peripheral Interface) Flash. The FPGA is used to build a system-on-chip integrating a soft processor (Xilinx MicroBlaze) and all the hardware blocks needed to handle the external peripherals and memory. The soft processor is used to handle image acquisition and all computational tasks need to compute the Veiling Luminance value. The advantages of this single chip FPGA implementation include the reduction of the hardware requirements, power consumption, and system complexity. The problem of the high dynamic range images have been addressed with multiple acquisitions at different exposure times. Vignetting, radial distortion and angular weighting, as required by veiling luminance definition, are handled by a single integer look-up table (LUT) access. Results are compared with a state of the art certified instrument.

Veiling Luminance estimation on FPGA-based embedded smart camera / Grana, Costantino; Borghesani, Daniele; Santinelli, Paolo; Cucchiara, Rita. - STAMPA. - (2012), pp. 334-339. ((Intervento presentato al convegno 2012 IEEE Intelligent Vehicles Symposium (IV) tenutosi a Alcalá de Henares, Spain nel Jun 3-7.

Veiling Luminance estimation on FPGA-based embedded smart camera

GRANA, Costantino;BORGHESANI, Daniele;SANTINELLI, PAOLO;CUCCHIARA, Rita
2012

Abstract

This paper describes the design and development of a Veiling Luminance estimation system based on the use of a CMOS image sensor, fully implemented on FPGA. The system is composed of the CMOS Image sensor, FPGA, DDR SDRAM, USB controller and SPI (Serial Peripheral Interface) Flash. The FPGA is used to build a system-on-chip integrating a soft processor (Xilinx MicroBlaze) and all the hardware blocks needed to handle the external peripherals and memory. The soft processor is used to handle image acquisition and all computational tasks need to compute the Veiling Luminance value. The advantages of this single chip FPGA implementation include the reduction of the hardware requirements, power consumption, and system complexity. The problem of the high dynamic range images have been addressed with multiple acquisitions at different exposure times. Vignetting, radial distortion and angular weighting, as required by veiling luminance definition, are handled by a single integer look-up table (LUT) access. Results are compared with a state of the art certified instrument.
2012 IEEE Intelligent Vehicles Symposium (IV)
Alcalá de Henares, Spain
Jun 3-7
334
339
Grana, Costantino; Borghesani, Daniele; Santinelli, Paolo; Cucchiara, Rita
Veiling Luminance estimation on FPGA-based embedded smart camera / Grana, Costantino; Borghesani, Daniele; Santinelli, Paolo; Cucchiara, Rita. - STAMPA. - (2012), pp. 334-339. ((Intervento presentato al convegno 2012 IEEE Intelligent Vehicles Symposium (IV) tenutosi a Alcalá de Henares, Spain nel Jun 3-7.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11380/764890
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