The influence of different layout parameters and of temperature on latch-up susceptibility has been studied on standard four-stripes test structures made using different processes: a standard n-well, a twin-tub and an epitaxial technology. Triggering characteristics of structures without guard rings can be fairly accurately predicted by two-dimensional simulations, performed by HFIELDS. Hysteresis effects in the holding characteristics are due to an uneven distribution of latch-up current within the structures, which has been detected by IR microscopy. Similar current redistribution effects can cause anomalies during pulsed measurements on CMOS integrated circuits. Three-diemsnional effects can be emulated by SPICE simulations.
The dependence of latch-up sensitivity on layout and technology features, as analyzed by electrical measurements, HFIELDS and SPICE simulations, and infrared microscopy characterization / E., Zanoni; G., Spiazzi; Pavan, Paolo; M., Cecchetti; M., Muschitiello. - STAMPA. - (1990), pp. 183-190. ( ESREF'90 Bari (I) 2-5 october 1990).
The dependence of latch-up sensitivity on layout and technology features, as analyzed by electrical measurements, HFIELDS and SPICE simulations, and infrared microscopy characterization
PAVAN, Paolo;
1990
Abstract
The influence of different layout parameters and of temperature on latch-up susceptibility has been studied on standard four-stripes test structures made using different processes: a standard n-well, a twin-tub and an epitaxial technology. Triggering characteristics of structures without guard rings can be fairly accurately predicted by two-dimensional simulations, performed by HFIELDS. Hysteresis effects in the holding characteristics are due to an uneven distribution of latch-up current within the structures, which has been detected by IR microscopy. Similar current redistribution effects can cause anomalies during pulsed measurements on CMOS integrated circuits. Three-diemsnional effects can be emulated by SPICE simulations.
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