Using this new module of Berkeley Reliability Tools (BERT), user can predict the error rate due to single event upset (SEU) in large circuits. The error rate model described here used a well established methodology, but for the first time a different choice is made on picking up the sensitive nodes, enabling a quick prediction even for large circuits.
Simulating single event upset error rate in large digital circuits / Pavan, Paolo; E., Minami; R., Tu; P. K., Ko; C., Hu. - STAMPA. - (1994), pp. 61-64. (Intervento presentato al convegno 5th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis tenutosi a Glasgow, Scotland nel 4-7 October 1994).
Simulating single event upset error rate in large digital circuits
PAVAN, Paolo;
1994
Abstract
Using this new module of Berkeley Reliability Tools (BERT), user can predict the error rate due to single event upset (SEU) in large circuits. The error rate model described here used a well established methodology, but for the first time a different choice is made on picking up the sensitive nodes, enabling a quick prediction even for large circuits.File | Dimensione | Formato | |
---|---|---|---|
C10.pdf
Accesso riservato
Tipologia:
Versione dell'autore revisionata e accettata per la pubblicazione
Dimensione
735.83 kB
Formato
Adobe PDF
|
735.83 kB | Adobe PDF | Visualizza/Apri Richiedi una copia |
Pubblicazioni consigliate
I metadati presenti in IRIS UNIMORE sono rilasciati con licenza Creative Commons CC0 1.0 Universal, mentre i file delle pubblicazioni sono rilasciati con licenza Attribuzione 4.0 Internazionale (CC BY 4.0), salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris