The dependence of the latch-up susceptibility on layout parameters is studied on four stripe structures made using different CMOS pro- cesses: a standard n-well, a twin-tub and twin-tub epitaxial technology. The correlation between triggering currents, well and substrate resistances and parasitic transistor gains is studied by means of emitter current triggering measurements and two- dimensional simulations using HFIELDS. Triggering currents higher than 250 mA are obtained on epitaxial structures with n+ guard-rings. Anomalies in triggering and holding electrical characteristics are caused by the three-dimensional distribution of the latch-up current, which is observed by IR microscopy. These anomalies can affect results of conventional latch-up testing methods.
Latch-up dc triggering and holding characteristics of n-well, twin-tub and epitaxial CMOS technologies / Pavan, Paolo; G., Spiazzi; E., Zanoni; M., Muschitiello; M., Cecchetti. - In: IEE PROCEEDINGS. PART G. CIRCUITS, DEVICES AND SYSTEMS. - ISSN 0956-3768. - STAMPA. - 138:(1991), pp. 604-612.