We present in this work and analysis of transiently triggered latch-up in test-structures fabricated using a twin-tub process implemented on two different substrates: a p-type and a p/p+ epitaxial one. Steady-state electrical characterization confirmed the well-known increased latch-up resistance of epitaxial structures with respect to standard ones. In this paper it is shown that, depending on the chosen electrical configuration, when latch-up is transiently triggered, epitaxial structures may have dynamic triggering currents lower that twin-tub ones. The influence of some layout variables on turn on threshold voltage has been investigated for all samples.
Transiently triggered latch-up in CMOS twin-tub and epitaxial technologies / Pavan, Paolo; P., Caprara; M., Stucchi; E., Zanoni. - In: QUALITY AND RELIABILITY ENGINEERING INTERNATIONAL. - ISSN 0748-8017. - STAMPA. - 8:(1992), pp. 273-278.
Transiently triggered latch-up in CMOS twin-tub and epitaxial technologies
PAVAN, Paolo;
1992
Abstract
We present in this work and analysis of transiently triggered latch-up in test-structures fabricated using a twin-tub process implemented on two different substrates: a p-type and a p/p+ epitaxial one. Steady-state electrical characterization confirmed the well-known increased latch-up resistance of epitaxial structures with respect to standard ones. In this paper it is shown that, depending on the chosen electrical configuration, when latch-up is transiently triggered, epitaxial structures may have dynamic triggering currents lower that twin-tub ones. The influence of some layout variables on turn on threshold voltage has been investigated for all samples.
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